Commit 3a35d903 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

S390 [liftoff]: Fix usage of offset register during load

zero extending the offset register must happen regardless
of the length of the offset_imm.

We can only use ip as the offset_reg as r0 and and r1
are being used as scratch later on.

Change-Id: I5517f974af40eb014b8e1f58f8e531909c4d466a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3794646
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/main@{#82087}
parent e2c3e4f2
...@@ -327,15 +327,18 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, ...@@ -327,15 +327,18 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
LoadType type, uint32_t* protected_load_pc, LoadType type, uint32_t* protected_load_pc,
bool is_load_mem, bool i64_offset) { bool is_load_mem, bool i64_offset) {
UseScratchRegisterScope temps(this); UseScratchRegisterScope temps(this);
if (offset_reg != no_reg && !i64_offset) {
// Clear the upper 32 bits of the 64 bit offset register.
llgfr(ip, offset_reg);
offset_reg = ip;
}
if (!is_int20(offset_imm)) { if (!is_int20(offset_imm)) {
mov(ip, Operand(offset_imm));
if (offset_reg != no_reg) { if (offset_reg != no_reg) {
if (!i64_offset) { mov(r0, Operand(offset_imm));
// Clear the upper 32 bits of the 64 bit offset register. AddS64(r0, offset_reg);
llgfr(r0, offset_reg); mov(ip, r0);
offset_reg = r0; } else {
} mov(ip, Operand(offset_imm));
AddS64(ip, offset_reg);
} }
offset_reg = ip; offset_reg = ip;
offset_imm = 0; offset_imm = 0;
......
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