Add FloatRegister names to RegisterConfiguration.

- Adds names for float registers to RegisterConfiguration and uses them
when we have the MachineRepresentation.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2030143002
Cr-Commit-Position: refs/heads/master@{#36712}

src/arm/assembler-arm.h

@@ -149,7 +149,20 @@ const Register no_reg = {Register::kCode_no_reg};
 
 // Single word VFP register.
 struct SwVfpRegister {
+  enum Code {
+#define REGISTER_CODE(R) kCode_##R,
+    FLOAT_REGISTERS(REGISTER_CODE)
+#undef REGISTER_CODE
+        kAfterLast,
+    kCode_no_reg = -1
+  };
+
+  static const int kMaxNumRegisters = Code::kAfterLast;
+
   static const int kSizeInBytes = 4;
+
+  const char* ToString();
+  bool IsAllocatable() const;
   bool is_valid() const { return 0 <= reg_code && reg_code < 32; }
   bool is(SwVfpRegister reg) const { return reg_code == reg.reg_code; }
   int code() const {

src/assembler.cc

@@ -130,7 +130,6 @@ bool Register::IsAllocatable() const {
               ->allocatable_general_codes_mask()) != 0;
 }
 
-
 const char* DoubleRegister::ToString() {
   // This is the mapping of allocation indices to registers.
   DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters);
@@ -145,6 +144,23 @@ bool DoubleRegister::IsAllocatable() const {
               ->allocatable_double_codes_mask()) != 0;
 }
 
+// FloatRegister is only a distinct type on ARM. On all other platforms it's
+// typedef'ed to DoubleRegister.
+#if V8_TARGET_ARCH_ARM
+const char* FloatRegister::ToString() {
+  // This is the mapping of allocation indices to registers.
+  DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters);
+  return RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)
+      ->GetFloatRegisterName(reg_code);
+}
+
+bool FloatRegister::IsAllocatable() const {
+  // TODO(bbudge) Update this once RegisterConfigutation handles aliasing.
+  return ((1 << reg_code) &
+          RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)
+              ->allocatable_double_codes_mask()) != 0;
+}
+#endif  // V8_TARGET_ARCH_ARM
 
 // -----------------------------------------------------------------------------
 // Common double constants.

src/compiler/graph-visualizer.cc

@@ -539,13 +539,13 @@ void GraphC1Visualizer::PrintLiveRange(const LiveRange* range, const char* type,
     os_ << vreg << ":" << range->relative_id() << " " << type;
     if (range->HasRegisterAssigned()) {
       AllocatedOperand op = AllocatedOperand::cast(range->GetAssignedOperand());
-      if (op.IsFPRegister()) {
-        DoubleRegister assigned_reg = op.GetDoubleRegister();
-        os_ << " \"" << assigned_reg.ToString() << "\"";
+      if (op.IsRegister()) {
+        os_ << " \"" << op.GetRegister().ToString() << "\"";
+      } else if (op.IsDoubleRegister()) {
+        os_ << " \"" << op.GetDoubleRegister().ToString() << "\"";
       } else {
-        DCHECK(op.IsRegister());
-        Register assigned_reg = op.GetRegister();
-        os_ << " \"" << assigned_reg.ToString() << "\"";
+        DCHECK(op.IsFloatRegister());
+        os_ << " \"" << op.GetFloatRegister().ToString() << "\"";
       }
     } else if (range->spilled()) {
       const TopLevelLiveRange* top = range->TopLevel();

src/compiler/instruction.cc

@@ -126,15 +126,16 @@ std::ostream& operator<<(std::ostream& os,
     case InstructionOperand::ALLOCATED: {
       LocationOperand allocated = LocationOperand::cast(op);
       if (op.IsStackSlot()) {
-        os << "[stack:" << LocationOperand::cast(op).index();
+        os << "[stack:" << allocated.index();
       } else if (op.IsFPStackSlot()) {
-        os << "[fp_stack:" << LocationOperand::cast(op).index();
+        os << "[fp_stack:" << allocated.index();
       } else if (op.IsRegister()) {
-        os << "[" << LocationOperand::cast(op).GetRegister().ToString() << "|R";
+        os << "[" << allocated.GetRegister().ToString() << "|R";
+      } else if (op.IsDoubleRegister()) {
+        os << "[" << allocated.GetDoubleRegister().ToString() << "|R";
       } else {
-        DCHECK(op.IsFPRegister());
-        os << "[" << LocationOperand::cast(op).GetDoubleRegister().ToString()
-           << "|R";
+        DCHECK(op.IsFloatRegister());
+        os << "[" << allocated.GetFloatRegister().ToString() << "|R";
       }
       if (allocated.IsExplicit()) {
         os << "|E";
@@ -247,7 +248,9 @@ ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep,
     : LocationOperand(EXPLICIT, kind, rep, index) {
   DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep),
                  Register::from_code(index).IsAllocatable());
-  DCHECK_IMPLIES(kind == REGISTER && IsFloatingPoint(rep),
+  DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat32),
+                 FloatRegister::from_code(index).IsAllocatable());
+  DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64),
                  DoubleRegister::from_code(index).IsAllocatable());
 }
 

src/register-configuration.cc

@@ -33,6 +33,12 @@ static const char* const kGeneralRegisterNames[] = {
 #undef REGISTER_NAME
 };
 
+static const char* const kFloatRegisterNames[] = {
+#define REGISTER_NAME(R) #R,
+    FLOAT_REGISTERS(REGISTER_NAME)
+#undef REGISTER_NAME
+};
+
 static const char* const kDoubleRegisterNames[] = {
 #define REGISTER_NAME(R) #R,
     DOUBLE_REGISTERS(REGISTER_NAME)
@@ -47,20 +53,16 @@ STATIC_ASSERT(RegisterConfiguration::kMaxFPRegisters >=
 class ArchDefaultRegisterConfiguration : public RegisterConfiguration {
  public:
   explicit ArchDefaultRegisterConfiguration(CompilerSelector compiler)
-      : RegisterConfiguration(Register::kNumRegisters,
-                              DoubleRegister::kMaxNumRegisters,
+      : RegisterConfiguration(
+            Register::kNumRegisters, DoubleRegister::kMaxNumRegisters,
 #if V8_TARGET_ARCH_IA32
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_X87
             kMaxAllocatableGeneralRegisterCount,
-                              compiler == TURBOFAN
-                                  ? 1
-                                  : kMaxAllocatableDoubleRegisterCount,
-                              compiler == TURBOFAN
-                                  ? 1
-                                  : kMaxAllocatableDoubleRegisterCount,
+            compiler == TURBOFAN ? 1 : kMaxAllocatableDoubleRegisterCount,
+            compiler == TURBOFAN ? 1 : kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_X64
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
@@ -71,10 +73,8 @@ class ArchDefaultRegisterConfiguration : public RegisterConfiguration {
                 : kMaxAllocatableGeneralRegisterCount,
             CpuFeatures::IsSupported(VFP32DREGS)
                 ? kMaxAllocatableDoubleRegisterCount
-                                  : (ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(
-                                        REGISTER_COUNT)0),
-                              ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(
-                                  REGISTER_COUNT)0,
+                : (ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(REGISTER_COUNT) 0),
+            ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(REGISTER_COUNT) 0,
 #elif V8_TARGET_ARCH_ARM64
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
@@ -99,7 +99,7 @@ class ArchDefaultRegisterConfiguration : public RegisterConfiguration {
 #error Unsupported target architecture.
 #endif
             kAllocatableGeneralCodes, kAllocatableDoubleCodes,
-                              kGeneralRegisterNames, kDoubleRegisterNames) {
+            kGeneralRegisterNames, kFloatRegisterNames, kDoubleRegisterNames) {
   }
 };
 
@@ -132,13 +132,13 @@ const RegisterConfiguration* RegisterConfiguration::ArchDefault(
              : &kDefaultRegisterConfigurationForCrankshaft.Get();
 }
 
-
 RegisterConfiguration::RegisterConfiguration(
     int num_general_registers, int num_double_registers,
     int num_allocatable_general_registers, int num_allocatable_double_registers,
     int num_allocatable_aliased_double_registers,
     const int* allocatable_general_codes, const int* allocatable_double_codes,
     const char* const* general_register_names,
+    const char* const* float_register_names,
     const char* const* double_register_names)
     : num_general_registers_(num_general_registers),
       num_double_registers_(num_double_registers),
@@ -151,6 +151,7 @@ RegisterConfiguration::RegisterConfiguration(
       allocatable_general_codes_(allocatable_general_codes),
       allocatable_double_codes_(allocatable_double_codes),
       general_register_names_(general_register_names),
+      float_register_names_(float_register_names),
       double_register_names_(double_register_names) {
   DCHECK(num_general_registers_ <= RegisterConfiguration::kMaxGeneralRegisters);
   DCHECK(num_double_registers_ <= RegisterConfiguration::kMaxFPRegisters);

src/register-configuration.h

@@ -34,6 +34,7 @@ class RegisterConfiguration {
                         const int* allocatable_general_codes,
                         const int* allocatable_double_codes,
                         char const* const* general_names,
+                        char const* const* float_names,
                         char const* const* double_names);
 
   int num_general_registers() const { return num_general_registers_; }
@@ -65,6 +66,9 @@ class RegisterConfiguration {
   const char* GetGeneralRegisterName(int code) const {
     return general_register_names_[code];
   }
+  const char* GetFloatRegisterName(int code) const {
+    return float_register_names_[code];
+  }
   const char* GetDoubleRegisterName(int code) const {
     return double_register_names_[code];
   }
@@ -86,6 +90,7 @@ class RegisterConfiguration {
   const int* allocatable_general_codes_;
   const int* allocatable_double_codes_;
   char const* const* general_register_names_;
+  char const* const* float_register_names_;
   char const* const* double_register_names_;
 };
 

test/unittests/compiler/instruction-sequence-unittest.cc

@@ -69,6 +69,7 @@ RegisterConfiguration* InstructionSequenceTest::config() {
         num_general_registers_, num_double_registers_, num_general_registers_,
         num_double_registers_, num_double_registers_, allocatable_codes,
         allocatable_double_codes, general_register_names_,
+        double_register_names_,  // float register names
         double_register_names_));
   }
   return config_.get();