Commit 392ee5d1 authored by sgjesse@chromium.org's avatar sgjesse@chromium.org

Fix ARM debug build

TBR=fschneider@chromium.org

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3216 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent 77a71c90
...@@ -142,14 +142,14 @@ void FastCodeGenerator::EmitReturnSequence(int position) { ...@@ -142,14 +142,14 @@ void FastCodeGenerator::EmitReturnSequence(int position) {
__ add(sp, sp, Operand(sp_delta)); __ add(sp, sp, Operand(sp_delta));
__ Jump(lr); __ Jump(lr);
// Check that the size of the code used for returning matches what is // Check that the size of the code used for returning matches what is
// expected by the debugger. The add instruction above is an addressing // expected by the debugger. The add instruction above is an addressing
// mode 1 instruction where there are restrictions on which immediate values // mode 1 instruction where there are restrictions on which immediate values
// can be encoded in the instruction and which immediate values requires // can be encoded in the instruction and which immediate values requires
// use of an additional instruction for moving the immediate to a temporary // use of an additional instruction for moving the immediate to a temporary
// register. // register.
ASSERT_EQ(expected_return_sequence_length, ASSERT_EQ(return_sequence_length,
masm_->InstructionsGeneratedSince(&check_exit_codesize)); masm_->InstructionsGeneratedSince(&check_exit_codesize));
} }
} }
......
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