PPC: Match -0 - x with sign bit flip.

Optimiation similar to what is done for x86

R=mbrandy@us.ibm.com

BUG=

Review URL: https://codereview.chromium.org/1072173002

Cr-Commit-Position: refs/heads/master@{#27718}

src/compiler/ppc/instruction-selector-ppc.cc

@@ -909,6 +909,13 @@ void InstructionSelector::VisitFloat64Add(Node* node) {
 
 
 void InstructionSelector::VisitFloat32Sub(Node* node) {
+  PPCOperandGenerator g(this);
+  Float32BinopMatcher m(node);
+  if (m.left().IsMinusZero()) {
+    Emit(kPPC_NegDouble, g.DefineAsRegister(node),
+         g.UseRegister(m.right().node()));
+    return;
+  }
   VisitRRR(this, kPPC_SubDouble, node);
 }
 
@@ -917,7 +924,8 @@ void InstructionSelector::VisitFloat64Sub(Node* node) {
   // TODO(mbrandy): detect multiply-subtract
   PPCOperandGenerator g(this);
   Float64BinopMatcher m(node);
-  if (m.left().IsMinusZero() && m.right().IsFloat64RoundDown() &&
+  if (m.left().IsMinusZero()) {
+    if (m.right().IsFloat64RoundDown() &&
         CanCover(m.node(), m.right().node())) {
       if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
           CanCover(m.right().node(), m.right().InputAt(0))) {
@@ -930,6 +938,10 @@ void InstructionSelector::VisitFloat64Sub(Node* node) {
         }
       }
     }
+    Emit(kPPC_NegDouble, g.DefineAsRegister(node),
+         g.UseRegister(m.right().node()));
+    return;
+  }
   VisitRRR(this, kPPC_SubDouble, node);
 }