Commit 34871edd authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

[wasm-simd][liftoff] Implement subset of v128.const

Partial implementation of v128.const, only the optimized case for all 0s
and all 1s. The other cases bailout to TurboFan for now, and will be
added in subsequent patches.

Bug: v8:9909
Change-Id: I3240c1c5f4259c45d51edca00fec37047bc1b3a5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2284212
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#68772}
parent 3fec0d91
...@@ -3269,6 +3269,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -3269,6 +3269,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
liftoff::F64x2Compare(this, dst, lhs, rhs, le); liftoff::F64x2Compare(this, dst, lhs, rhs, le);
} }
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
const uint8_t imms[16]) {
bailout(kSimd, "s128.const");
}
void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) { void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) {
vmvn(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(src)); vmvn(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(src));
} }
......
...@@ -2331,6 +2331,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -2331,6 +2331,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
Fcmge(dst.fp().V2D(), rhs.fp().V2D(), lhs.fp().V2D()); Fcmge(dst.fp().V2D(), rhs.fp().V2D(), lhs.fp().V2D());
} }
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
const uint8_t imms[16]) {
bailout(kSimd, "s128.const");
}
void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) { void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) {
Mvn(dst.fp().V16B(), src.fp().V16B()); Mvn(dst.fp().V16B(), src.fp().V16B());
} }
......
...@@ -2832,6 +2832,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -2832,6 +2832,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
rhs); rhs);
} }
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
const uint8_t imms[16]) {
bailout(kSimd, "s128.const");
}
void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) { void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) {
if (dst.fp() != src.fp()) { if (dst.fp() != src.fp()) {
Pcmpeqd(dst.fp(), dst.fp()); Pcmpeqd(dst.fp(), dst.fp());
......
...@@ -818,6 +818,7 @@ class LiftoffAssembler : public TurboAssembler { ...@@ -818,6 +818,7 @@ class LiftoffAssembler : public TurboAssembler {
LiftoffRegister rhs); LiftoffRegister rhs);
inline void emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, inline void emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs); LiftoffRegister rhs);
inline void emit_s128_const(LiftoffRegister dst, const uint8_t imms[16]);
inline void emit_s128_not(LiftoffRegister dst, LiftoffRegister src); inline void emit_s128_not(LiftoffRegister dst, LiftoffRegister src);
inline void emit_s128_and(LiftoffRegister dst, LiftoffRegister lhs, inline void emit_s128_and(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs); LiftoffRegister rhs);
......
...@@ -2949,7 +2949,21 @@ class LiftoffCompiler { ...@@ -2949,7 +2949,21 @@ class LiftoffCompiler {
void S128Const(FullDecoder* decoder, const Simd128Immediate<validate>& imm, void S128Const(FullDecoder* decoder, const Simd128Immediate<validate>& imm,
Value* result) { Value* result) {
unsupported(decoder, kSimd, "simd"); constexpr RegClass result_rc = reg_class_for(ValueType::kS128);
LiftoffRegister dst = __ GetUnusedRegister(result_rc, {});
bool all_zeroes = std::all_of(std::begin(imm.value), std::end(imm.value),
[](uint8_t v) { return v == 0; });
bool all_ones = std::all_of(std::begin(imm.value), std::end(imm.value),
[](uint8_t v) { return v == 0xff; });
if (all_zeroes) {
__ LiftoffAssembler::emit_s128_xor(dst, dst, dst);
} else if (all_ones) {
// Any SIMD eq will work, i32x4 is efficient on all archs.
__ LiftoffAssembler::emit_i32x4_eq(dst, dst, dst);
} else {
__ LiftoffAssembler::emit_s128_const(dst, imm.value);
}
__ PushRegister(kWasmS128, dst);
} }
void Simd8x16ShuffleOp(FullDecoder* decoder, void Simd8x16ShuffleOp(FullDecoder* decoder,
......
...@@ -2547,6 +2547,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -2547,6 +2547,11 @@ void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
rhs); rhs);
} }
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
const uint8_t imms[16]) {
bailout(kSimd, "s128.const");
}
void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) { void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) {
if (dst.fp() != src.fp()) { if (dst.fp() != src.fp()) {
Pcmpeqd(dst.fp(), dst.fp()); Pcmpeqd(dst.fp(), dst.fp());
......
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