[wasm][ia32] Add S8x16Shuffle

Change-Id: I9a78e0a8f673f311414f72055958c52d3c2cb0cd
Reviewed-on: https://chromium-review.googlesource.com/908256
Commit-Queue: Kanghua Yu <kanghua.yu@intel.com>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Reviewed-by: Aseem Garg <aseemgarg@chromium.org>
Cr-Commit-Position: refs/heads/master@{#52166}

src/compiler/ia32/code-generator-ia32.cc

@@ -2995,6 +2995,51 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vxorps(dst, dst, i.InputSimd128Register(2));
       break;
     }
+    case kIA32S8x16Shuffle: {
+      XMMRegister dst = i.OutputSimd128Register();
+      Register tmp = i.TempRegister(0);
+      // Prepare 16-byte boundary buffer for shuffle control mask
+      __ mov(tmp, esp);
+      __ movups(dst, i.InputOperand(0));
+      __ and_(esp, -16);
+      if (instr->InputCount() == 5) {  // only one input operand
+        for (int j = 4; j > 0; j--) {
+          uint32_t mask = i.InputUint32(j);
+          __ push(Immediate(mask));
+        }
+        __ Pshufb(dst, Operand(esp, 0));
+      } else {  // two input operands
+        DCHECK_EQ(6, instr->InputCount());
+        for (int j = 5; j > 1; j--) {
+          uint32_t lanes = i.InputUint32(j);
+          uint32_t mask = 0;
+          for (int k = 0; k < 32; k += 8) {
+            uint8_t lane = lanes >> k;
+            mask |= (lane < kSimd128Size ? lane : 0x80) << k;
+          }
+          __ push(Immediate(mask));
+        }
+        __ Pshufb(dst, Operand(esp, 0));
+        __ movups(kScratchDoubleReg, i.InputOperand(1));
+        for (int j = 5; j > 1; j--) {
+          uint32_t lanes = i.InputUint32(j);
+          uint32_t mask = 0;
+          for (int k = 0; k < 32; k += 8) {
+            uint8_t lane = lanes >> k;
+            mask |= (lane >= kSimd128Size ? (lane & 0xF) : 0x80) << k;
+          }
+          __ push(Immediate(mask));
+        }
+        __ Pshufb(kScratchDoubleReg, Operand(esp, 0));
+        __ por(dst, kScratchDoubleReg);
+      }
+      __ mov(esp, tmp);
+      break;
+    }
+    case kIA32S32x4Swizzle: {
+      __ Pshufd(i.OutputSimd128Register(), i.InputOperand(0), i.InputInt8(1));
+      break;
+    }
     case kIA32StackCheck: {
       ExternalReference const stack_limit =
           ExternalReference::address_of_stack_limit(__ isolate());

src/compiler/ia32/instruction-codes-ia32.h

@@ -280,7 +280,9 @@ namespace compiler {
   V(SSES128Xor)                    \
   V(AVXS128Xor)                    \
   V(SSES128Select)                 \
-  V(AVXS128Select)
+  V(AVXS128Select)                 \
+  V(IA32S8x16Shuffle)              \
+  V(IA32S32x4Swizzle)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes

src/compiler/ia32/instruction-scheduler-ia32.cc

@@ -263,6 +263,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kAVXS128Xor:
     case kSSES128Select:
     case kAVXS128Select:
+    case kIA32S8x16Shuffle:
+    case kIA32S32x4Swizzle:
       return (instr->addressing_mode() == kMode_None)
           ? kNoOpcodeFlags
           : kIsLoadOperation | kHasSideEffect;

src/compiler/ia32/instruction-selector-ia32.cc

@@ -1967,6 +1967,43 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   UNREACHABLE();
 }
 
+void InstructionSelector::VisitS8x16Shuffle(Node* node) {
+  static const int kMaxSwizzleIndex = 15;
+  static const int kMaxShuffleIndex = 31;
+  const uint8_t* shuffle = OpParameter<uint8_t*>(node->op());
+  uint8_t mask = CanonicalizeShuffle(node);
+  uint8_t shuffle32x4[4];
+  IA32OperandGenerator g(this);
+  InstructionOperand output = g.DefineAsRegister(node);
+  InstructionOperand inputs[6];
+  InstructionOperand temps[1];
+  size_t input_count = 0;
+  Node* input0 = node->InputAt(0);
+  Node* input1 = node->InputAt(1);
+  if (mask == kMaxSwizzleIndex) {
+    if (TryMatch32x4Shuffle(shuffle, shuffle32x4)) {
+      Emit(kIA32S32x4Swizzle, output, g.Use(input0),
+           g.UseImmediate((shuffle32x4[0] & 3) | ((shuffle32x4[1] & 3) << 2) |
+                          ((shuffle32x4[2] & 3) << 4) |
+                          ((shuffle32x4[3] & 3) << 6)));
+      return;
+    }
+    // TODO(ia32): handle non 32x4 swizzles here
+    inputs[input_count++] = g.Use(input0);
+  } else {
+    DCHECK_EQ(kMaxShuffleIndex, mask);
+    USE(kMaxShuffleIndex);
+    inputs[input_count++] = g.Use(input0);
+    inputs[input_count++] = g.Use(input1);
+  }
+  inputs[input_count++] = g.UseImmediate(Pack4Lanes(shuffle, mask));
+  inputs[input_count++] = g.UseImmediate(Pack4Lanes(shuffle + 4, mask));
+  inputs[input_count++] = g.UseImmediate(Pack4Lanes(shuffle + 8, mask));
+  inputs[input_count++] = g.UseImmediate(Pack4Lanes(shuffle + 12, mask));
+  temps[0] = g.TempRegister();
+  Emit(kIA32S8x16Shuffle, 1, &output, input_count, inputs, 1, temps);
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {

src/compiler/instruction-selector.cc

@@ -2421,13 +2421,13 @@ void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16Mul(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
         // && !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_IA32
 
 #if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
     !V8_TARGET_ARCH_MIPS64
-void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
-
 void InstructionSelector::VisitS1x4AnyTrue(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitS1x4AllTrue(Node* node) { UNIMPLEMENTED(); }

src/compiler/simd-scalar-lowering.cc

@@ -184,7 +184,8 @@ void SimdScalarLowering::LowerGraph() {
   V(I8x16LtS)                     \
   V(I8x16LeS)                     \
   V(I8x16LtU)                     \
-  V(I8x16LeU)
+  V(I8x16LeU)                     \
+  V(S8x16Shuffle)
 
 MachineType SimdScalarLowering::MachineTypeFrom(SimdType simdType) {
   switch (simdType) {
@@ -1172,6 +1173,19 @@ void SimdScalarLowering::LowerNode(Node* node) {
       ReplaceNode(node, rep_node, num_lanes);
       break;
     }
+    case IrOpcode::kS8x16Shuffle: {
+      DCHECK_EQ(2, node->InputCount());
+      const uint8_t* shuffle = OpParameter<uint8_t*>(node->op());
+      Node** rep_left = GetReplacementsWithType(node->InputAt(0), rep_type);
+      Node** rep_right = GetReplacementsWithType(node->InputAt(1), rep_type);
+      Node** rep_node = zone()->NewArray<Node*>(16);
+      for (int i = 0; i < 16; i++) {
+        int lane = shuffle[i];
+        rep_node[i] = lane < 16 ? rep_left[lane] : rep_right[lane - 16];
+      }
+      ReplaceNode(node, rep_node, 16);
+      break;
+    }
     default: { DefaultLowering(node); }
   }
 }

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1574,8 +1574,6 @@ WASM_SIMD_NON_CANONICAL_SELECT_TEST(32x4)
 WASM_SIMD_NON_CANONICAL_SELECT_TEST(16x8)
 WASM_SIMD_NON_CANONICAL_SELECT_TEST(8x16)
 
-#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
-    V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
 // Test binary ops with two lane test patterns, all lanes distinct.
 template <typename T>
 void RunBinaryLaneOpTest(
@@ -1609,6 +1607,8 @@ void RunBinaryLaneOpTest(
   }
 }
 
+#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
+    V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
 WASM_SIMD_TEST(I32x4AddHoriz) {
   RunBinaryLaneOpTest<int32_t>(lower_simd, kExprI32x4AddHoriz, {{1, 5, 9, 13}});
 }
@@ -1626,10 +1626,10 @@ WASM_SIMD_TEST(F32x4AddHoriz) {
         // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
 
 #if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
-    V8_TARGET_ARCH_MIPS64
+    V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
 // Test some regular shuffles that may have special handling on some targets.
 // Test a normal and unary versions (where second operand isn't used).
-WASM_SIMD_COMPILED_TEST(S32x4Dup) {
+WASM_SIMD_TEST(S32x4Dup) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{16, 17, 18, 19, 16, 17, 18, 19, 16, 17, 18, 19, 16, 17, 18, 19}});
@@ -1638,7 +1638,7 @@ WASM_SIMD_COMPILED_TEST(S32x4Dup) {
       {{4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 6, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S32x4ZipLeft) {
+WASM_SIMD_TEST(S32x4ZipLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}});
@@ -1647,7 +1647,7 @@ WASM_SIMD_COMPILED_TEST(S32x4ZipLeft) {
       {{0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 6, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S32x4ZipRight) {
+WASM_SIMD_TEST(S32x4ZipRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}});
@@ -1656,7 +1656,7 @@ WASM_SIMD_COMPILED_TEST(S32x4ZipRight) {
       {{8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15, 12, 13, 14, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S32x4UnzipLeft) {
+WASM_SIMD_TEST(S32x4UnzipLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}});
@@ -1665,7 +1665,7 @@ WASM_SIMD_COMPILED_TEST(S32x4UnzipLeft) {
       {{0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 8, 9, 10, 11}});
 }
 
-WASM_SIMD_COMPILED_TEST(S32x4UnzipRight) {
+WASM_SIMD_TEST(S32x4UnzipRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}});
@@ -1674,7 +1674,7 @@ WASM_SIMD_COMPILED_TEST(S32x4UnzipRight) {
       {{4, 5, 6, 7, 12, 13, 14, 15, 4, 5, 6, 7, 12, 13, 14, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S32x4TransposeLeft) {
+WASM_SIMD_TEST(S32x4TransposeLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27}});
@@ -1683,7 +1683,7 @@ WASM_SIMD_COMPILED_TEST(S32x4TransposeLeft) {
       {{0, 1, 2, 3, 0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11}});
 }
 
-WASM_SIMD_COMPILED_TEST(S32x4TransposeRight) {
+WASM_SIMD_TEST(S32x4TransposeRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31}});
@@ -1693,14 +1693,14 @@ WASM_SIMD_COMPILED_TEST(S32x4TransposeRight) {
 }
 
 // Reverses are only unary.
-WASM_SIMD_COMPILED_TEST(S32x2Reverse) {
+WASM_SIMD_TEST(S32x2Reverse) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11}});
 }
 
 // Test irregular shuffle.
-WASM_SIMD_COMPILED_TEST(S32x4Irregular) {
+WASM_SIMD_TEST(S32x4Irregular) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 2, 3, 16, 17, 18, 19, 16, 17, 18, 19, 20, 21, 22, 23}});
@@ -1709,7 +1709,7 @@ WASM_SIMD_COMPILED_TEST(S32x4Irregular) {
       {{0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8Dup) {
+WASM_SIMD_TEST(S16x8Dup) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{18, 19, 18, 19, 18, 19, 18, 19, 18, 19, 18, 19, 18, 19, 18, 19}});
@@ -1718,7 +1718,7 @@ WASM_SIMD_COMPILED_TEST(S16x8Dup) {
       {{6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8ZipLeft) {
+WASM_SIMD_TEST(S16x8ZipLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}});
@@ -1727,7 +1727,7 @@ WASM_SIMD_COMPILED_TEST(S16x8ZipLeft) {
       {{0, 1, 0, 1, 2, 3, 2, 3, 4, 5, 4, 5, 6, 7, 6, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8ZipRight) {
+WASM_SIMD_TEST(S16x8ZipRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}});
@@ -1736,7 +1736,7 @@ WASM_SIMD_COMPILED_TEST(S16x8ZipRight) {
       {{8, 9, 8, 9, 10, 11, 10, 11, 12, 13, 12, 13, 14, 15, 14, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8UnzipLeft) {
+WASM_SIMD_TEST(S16x8UnzipLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29}});
@@ -1745,7 +1745,7 @@ WASM_SIMD_COMPILED_TEST(S16x8UnzipLeft) {
       {{0, 1, 4, 5, 8, 9, 12, 13, 0, 1, 4, 5, 8, 9, 12, 13}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8UnzipRight) {
+WASM_SIMD_TEST(S16x8UnzipRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31}});
@@ -1754,7 +1754,7 @@ WASM_SIMD_COMPILED_TEST(S16x8UnzipRight) {
       {{2, 3, 6, 7, 10, 11, 14, 15, 2, 3, 6, 7, 10, 11, 14, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8TransposeLeft) {
+WASM_SIMD_TEST(S16x8TransposeLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 16, 17, 4, 5, 20, 21, 8, 9, 24, 25, 12, 13, 28, 29}});
@@ -1763,7 +1763,7 @@ WASM_SIMD_COMPILED_TEST(S16x8TransposeLeft) {
       {{0, 1, 0, 1, 4, 5, 4, 5, 8, 9, 8, 9, 12, 13, 12, 13}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8TransposeRight) {
+WASM_SIMD_TEST(S16x8TransposeRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{2, 3, 18, 19, 6, 7, 22, 23, 10, 11, 26, 27, 14, 15, 30, 31}});
@@ -1772,19 +1772,19 @@ WASM_SIMD_COMPILED_TEST(S16x8TransposeRight) {
       {{2, 3, 2, 3, 6, 7, 6, 7, 10, 11, 10, 11, 14, 15, 14, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x4Reverse) {
+WASM_SIMD_TEST(S16x4Reverse) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x2Reverse) {
+WASM_SIMD_TEST(S16x2Reverse) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13}});
 }
 
-WASM_SIMD_COMPILED_TEST(S16x8Irregular) {
+WASM_SIMD_TEST(S16x8Irregular) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 1, 16, 17, 16, 17, 0, 1, 4, 5, 20, 21, 6, 7, 22, 23}});
@@ -1793,7 +1793,7 @@ WASM_SIMD_COMPILED_TEST(S16x8Irregular) {
       {{0, 1, 0, 1, 0, 1, 0, 1, 4, 5, 4, 5, 6, 7, 6, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16Dup) {
+WASM_SIMD_TEST(S8x16Dup) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19}});
@@ -1802,7 +1802,7 @@ WASM_SIMD_COMPILED_TEST(S8x16Dup) {
       {{7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16ZipLeft) {
+WASM_SIMD_TEST(S8x16ZipLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}});
@@ -1811,7 +1811,7 @@ WASM_SIMD_COMPILED_TEST(S8x16ZipLeft) {
       {{0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16ZipRight) {
+WASM_SIMD_TEST(S8x16ZipRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}});
@@ -1820,7 +1820,7 @@ WASM_SIMD_COMPILED_TEST(S8x16ZipRight) {
       {{8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16UnzipLeft) {
+WASM_SIMD_TEST(S8x16UnzipLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30}});
@@ -1829,7 +1829,7 @@ WASM_SIMD_COMPILED_TEST(S8x16UnzipLeft) {
       {{0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16UnzipRight) {
+WASM_SIMD_TEST(S8x16UnzipRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}});
@@ -1838,7 +1838,7 @@ WASM_SIMD_COMPILED_TEST(S8x16UnzipRight) {
       {{1, 3, 5, 7, 9, 11, 13, 15, 1, 3, 5, 7, 9, 11, 13, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16TransposeLeft) {
+WASM_SIMD_TEST(S8x16TransposeLeft) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30}});
@@ -1847,7 +1847,7 @@ WASM_SIMD_COMPILED_TEST(S8x16TransposeLeft) {
       {{0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16TransposeRight) {
+WASM_SIMD_TEST(S8x16TransposeRight) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31}});
@@ -1856,25 +1856,25 @@ WASM_SIMD_COMPILED_TEST(S8x16TransposeRight) {
       {{1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x8Reverse) {
+WASM_SIMD_TEST(S8x8Reverse) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x4Reverse) {
+WASM_SIMD_TEST(S8x4Reverse) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x2Reverse) {
+WASM_SIMD_TEST(S8x2Reverse) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}});
 }
 
-WASM_SIMD_COMPILED_TEST(S8x16Irregular) {
+WASM_SIMD_TEST(S8x16Irregular) {
   RunBinaryLaneOpTest<int8_t>(
       lower_simd, kExprS8x16Shuffle,
       {{0, 16, 0, 16, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}});
@@ -1885,7 +1885,7 @@ WASM_SIMD_COMPILED_TEST(S8x16Irregular) {
 
 // Test shuffles that concatenate the two vectors.
 
-WASM_SIMD_COMPILED_TEST(S8x16Concat) {
+WASM_SIMD_TEST(S8x16Concat) {
   static const int kLanes = 16;
   std::array<uint8_t, kLanes> expected;
   for (int bias = 1; bias < kLanes; bias++) {
@@ -1901,7 +1901,11 @@ WASM_SIMD_COMPILED_TEST(S8x16Concat) {
     RunBinaryLaneOpTest(lower_simd, kExprS8x16Shuffle, expected);
   }
 }
+#endif  // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
+        // V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
 
+#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
+    V8_TARGET_ARCH_MIPS64
 // Boolean unary operations are 'AllTrue' and 'AnyTrue', which return an integer
 // result. Use relational ops on numeric vectors to create the boolean vector
 // test inputs. Test inputs with all true, all false, one true, and one false.