Commit 32d3c92d authored by Junliang Yan's avatar Junliang Yan Committed by Commit Bot

s390x: [liftoff] cleanup floating point functions

Change-Id: I0ef9381fd2c68414c10cb14eb678507b7f12673b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2844074Reviewed-by: 's avatarMilad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#74111}
parent c8f1b36d
...@@ -1398,9 +1398,19 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) { ...@@ -1398,9 +1398,19 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
LFR_TO_REG, LFR_TO_REG, USE, , void) \ LFR_TO_REG, LFR_TO_REG, USE, , void) \
V(i64_ctz, CountTrailingZerosU64, LiftoffRegister, LiftoffRegister, \ V(i64_ctz, CountTrailingZerosU64, LiftoffRegister, LiftoffRegister, \
LFR_TO_REG, LFR_TO_REG, USE, , void) \ LFR_TO_REG, LFR_TO_REG, USE, , void) \
V(f32_ceil, CeilF32, DoubleRegister, DoubleRegister, , , USE, true, bool) \
V(f32_floor, FloorF32, DoubleRegister, DoubleRegister, , , USE, true, bool) \
V(f32_trunc, TruncF32, DoubleRegister, DoubleRegister, , , USE, true, bool) \
V(f32_nearest_int, NearestIntF32, DoubleRegister, DoubleRegister, , , USE, \
true, bool) \
V(f32_abs, lpebr, DoubleRegister, DoubleRegister, , , USE, , void) \ V(f32_abs, lpebr, DoubleRegister, DoubleRegister, , , USE, , void) \
V(f32_neg, lcebr, DoubleRegister, DoubleRegister, , , USE, , void) \ V(f32_neg, lcebr, DoubleRegister, DoubleRegister, , , USE, , void) \
V(f32_sqrt, sqebr, DoubleRegister, DoubleRegister, , , USE, , void) \ V(f32_sqrt, sqebr, DoubleRegister, DoubleRegister, , , USE, , void) \
V(f64_ceil, CeilF64, DoubleRegister, DoubleRegister, , , USE, true, bool) \
V(f64_floor, FloorF64, DoubleRegister, DoubleRegister, , , USE, true, bool) \
V(f64_trunc, TruncF64, DoubleRegister, DoubleRegister, , , USE, true, bool) \
V(f64_nearest_int, NearestIntF64, DoubleRegister, DoubleRegister, , , USE, \
true, bool) \
V(f64_abs, lpdbr, DoubleRegister, DoubleRegister, , , USE, , void) \ V(f64_abs, lpdbr, DoubleRegister, DoubleRegister, , , USE, , void) \
V(f64_neg, lcdbr, DoubleRegister, DoubleRegister, , , USE, , void) \ V(f64_neg, lcdbr, DoubleRegister, DoubleRegister, , , USE, , void) \
V(f64_sqrt, sqdbr, DoubleRegister, DoubleRegister, , , USE, , void) V(f64_sqrt, sqdbr, DoubleRegister, DoubleRegister, , , USE, , void)
...@@ -1421,6 +1431,14 @@ UNOP_LIST(EMIT_UNOP_FUNCTION) ...@@ -1421,6 +1431,14 @@ UNOP_LIST(EMIT_UNOP_FUNCTION)
// V(name, instr, dtype, stype1, stype2, dcast, scast1, scast2, rcast, // V(name, instr, dtype, stype1, stype2, dcast, scast1, scast2, rcast,
// return_val, return_type) // return_val, return_type)
#define BINOP_LIST(V) \ #define BINOP_LIST(V) \
V(f32_min, FloatMin, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
USE, , void) \
V(f32_max, FloatMax, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
USE, , void) \
V(f64_min, DoubleMin, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
USE, , void) \
V(f64_max, DoubleMax, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
USE, , void) \
V(f64_add, AddF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \ V(f64_add, AddF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
USE, , void) \ USE, , void) \
V(f64_sub, SubF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \ V(f64_sub, SubF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
...@@ -1515,68 +1533,6 @@ BINOP_LIST(EMIT_BINOP_FUNCTION) ...@@ -1515,68 +1533,6 @@ BINOP_LIST(EMIT_BINOP_FUNCTION)
#undef REGISTER_AND_WITH_1F #undef REGISTER_AND_WITH_1F
#undef LFR_TO_REG #undef LFR_TO_REG
bool LiftoffAssembler::emit_f32_ceil(DoubleRegister dst, DoubleRegister src) {
CeilF32(dst, src);
return true;
}
bool LiftoffAssembler::emit_f32_floor(DoubleRegister dst, DoubleRegister src) {
FloorF32(dst, src);
return true;
}
bool LiftoffAssembler::emit_f32_trunc(DoubleRegister dst, DoubleRegister src) {
TruncF32(dst, src);
return true;
}
bool LiftoffAssembler::emit_f32_nearest_int(DoubleRegister dst,
DoubleRegister src) {
NearestIntF32(dst, src);
return true;
}
void LiftoffAssembler::emit_f64_min(DoubleRegister dst, DoubleRegister lhs,
DoubleRegister rhs) {
DoubleMin(dst, lhs, rhs);
}
void LiftoffAssembler::emit_f32_min(DoubleRegister dst, DoubleRegister lhs,
DoubleRegister rhs) {
FloatMin(dst, lhs, rhs);
}
bool LiftoffAssembler::emit_f64_ceil(DoubleRegister dst, DoubleRegister src) {
CeilF64(dst, src);
return true;
}
bool LiftoffAssembler::emit_f64_floor(DoubleRegister dst, DoubleRegister src) {
FloorF64(dst, src);
return true;
}
bool LiftoffAssembler::emit_f64_trunc(DoubleRegister dst, DoubleRegister src) {
TruncF64(dst, src);
return true;
}
bool LiftoffAssembler::emit_f64_nearest_int(DoubleRegister dst,
DoubleRegister src) {
NearestIntF64(dst, src);
return true;
}
void LiftoffAssembler::emit_f64_max(DoubleRegister dst, DoubleRegister lhs,
DoubleRegister rhs) {
DoubleMax(dst, lhs, rhs);
}
void LiftoffAssembler::emit_f32_max(DoubleRegister dst, DoubleRegister lhs,
DoubleRegister rhs) {
FloatMax(dst, lhs, rhs);
}
void LiftoffAssembler::emit_i32_divs(Register dst, Register lhs, Register rhs, void LiftoffAssembler::emit_i32_divs(Register dst, Register lhs, Register rhs,
Label* trap_div_by_zero, Label* trap_div_by_zero,
Label* trap_div_unrepresentable) { Label* trap_div_unrepresentable) {
......
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