Commit 3288fb63 authored by Ng Zhi An's avatar Ng Zhi An Committed by V8 LUCI CQ

[ia32] Fix some instruction code names

F64x2ExtractLane and F64x2ReplaceLane were missing the IA32 prefix that
is used by all the other instruction codes.

Bug: v8:12244
Change-Id: Ib99cd9b62161a13305ad01d6e7e0aa82046dd25a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3255662Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#77808}
parent 4f1dbc72
...@@ -1759,12 +1759,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -1759,12 +1759,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Movddup(i.OutputSimd128Register(), i.InputDoubleRegister(0)); __ Movddup(i.OutputSimd128Register(), i.InputDoubleRegister(0));
break; break;
} }
case kF64x2ExtractLane: { case kIA32F64x2ExtractLane: {
__ F64x2ExtractLane(i.OutputDoubleRegister(), i.InputDoubleRegister(0), __ F64x2ExtractLane(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
i.InputUint8(1)); i.InputUint8(1));
break; break;
} }
case kF64x2ReplaceLane: { case kIA32F64x2ReplaceLane: {
__ F64x2ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), __ F64x2ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputDoubleRegister(2), i.InputInt8(1)); i.InputDoubleRegister(2), i.InputInt8(1));
break; break;
......
...@@ -111,8 +111,8 @@ namespace compiler { ...@@ -111,8 +111,8 @@ namespace compiler {
V(IA32I32x4TruncF32x4U) \ V(IA32I32x4TruncF32x4U) \
V(IA32I32x4TruncF64x2UZero) \ V(IA32I32x4TruncF64x2UZero) \
V(IA32F64x2Splat) \ V(IA32F64x2Splat) \
V(F64x2ExtractLane) \ V(IA32F64x2ExtractLane) \
V(F64x2ReplaceLane) \ V(IA32F64x2ReplaceLane) \
V(IA32F64x2Sqrt) \ V(IA32F64x2Sqrt) \
V(IA32F64x2Add) \ V(IA32F64x2Add) \
V(IA32F64x2Sub) \ V(IA32F64x2Sub) \
......
...@@ -95,8 +95,8 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -95,8 +95,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kIA32I32x4TruncF32x4U: case kIA32I32x4TruncF32x4U:
case kIA32I32x4TruncF64x2UZero: case kIA32I32x4TruncF64x2UZero:
case kIA32F64x2Splat: case kIA32F64x2Splat:
case kF64x2ExtractLane: case kIA32F64x2ExtractLane:
case kF64x2ReplaceLane: case kIA32F64x2ReplaceLane:
case kIA32F64x2Sqrt: case kIA32F64x2Sqrt:
case kIA32F64x2Add: case kIA32F64x2Add:
case kIA32F64x2Sub: case kIA32F64x2Sub:
......
...@@ -2449,7 +2449,7 @@ void InstructionSelector::VisitF64x2Splat(Node* node) { ...@@ -2449,7 +2449,7 @@ void InstructionSelector::VisitF64x2Splat(Node* node) {
} }
void InstructionSelector::VisitF64x2ExtractLane(Node* node) { void InstructionSelector::VisitF64x2ExtractLane(Node* node) {
VisitRRISimd(this, node, kF64x2ExtractLane, kF64x2ExtractLane); VisitRRISimd(this, node, kIA32F64x2ExtractLane, kIA32F64x2ExtractLane);
} }
void InstructionSelector::VisitI64x2SplatI32Pair(Node* node) { void InstructionSelector::VisitI64x2SplatI32Pair(Node* node) {
...@@ -2625,7 +2625,7 @@ void InstructionSelector::VisitF64x2ReplaceLane(Node* node) { ...@@ -2625,7 +2625,7 @@ void InstructionSelector::VisitF64x2ReplaceLane(Node* node) {
// When no-AVX, define dst == src to save a move. // When no-AVX, define dst == src to save a move.
InstructionOperand dst = InstructionOperand dst =
IsSupported(AVX) ? g.DefineAsRegister(node) : g.DefineSameAsFirst(node); IsSupported(AVX) ? g.DefineAsRegister(node) : g.DefineSameAsFirst(node);
Emit(kF64x2ReplaceLane, dst, g.UseRegister(node->InputAt(0)), Emit(kIA32F64x2ReplaceLane, dst, g.UseRegister(node->InputAt(0)),
g.UseImmediate(lane), g.UseRegister(node->InputAt(1))); g.UseImmediate(lane), g.UseRegister(node->InputAt(1)));
} }
......
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