Reduce some duplication in the x64 assembler

Bug: v8:9810
Change-Id: I585d35d01acf77d15ccb0e7334786d15ba07fb41
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1876634
Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64660}

src/codegen/x64/assembler-x64.cc

@@ -2802,45 +2802,6 @@ void Assembler::movdqu(XMMRegister dst, Operand src) {
   emit_sse_operand(dst, src);
 }
 
-void Assembler::extractps(Register dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x17);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
-void Assembler::pextrb(Register dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x14);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
-void Assembler::pextrb(Operand dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x14);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
 void Assembler::pinsrw(XMMRegister dst, Register src, int8_t imm8) {
   DCHECK(is_uint8(imm8));
   EnsureSpace ensure_space(this);
@@ -2863,56 +2824,6 @@ void Assembler::pinsrw(XMMRegister dst, Operand src, int8_t imm8) {
   emit(imm8);
 }
 
-void Assembler::pextrw(Register dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x15);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
-void Assembler::pextrw(Operand dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x15);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
-void Assembler::pextrd(Register dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x16);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
-void Assembler::pextrd(Operand dst, XMMRegister src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(src, dst);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x16);
-  emit_sse_operand(src, dst);
-  emit(imm8);
-}
-
 void Assembler::pextrq(Register dst, XMMRegister src, int8_t imm8) {
   DCHECK(IsEnabled(SSE4_1));
   EnsureSpace ensure_space(this);
@@ -2939,6 +2850,7 @@ void Assembler::pinsrq(XMMRegister dst, Register src, int8_t imm8) {
 
 void Assembler::pinsrq(XMMRegister dst, Operand src, int8_t imm8) {
   DCHECK(IsEnabled(SSE4_1));
+  DCHECK(is_uint8(imm8));
   EnsureSpace ensure_space(this);
   emit(0x66);
   emit_rex_64(dst, src);
@@ -2950,76 +2862,34 @@ void Assembler::pinsrq(XMMRegister dst, Operand src, int8_t imm8) {
 }
 
 void Assembler::pinsrd(XMMRegister dst, Register src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x22);
-  emit_sse_operand(dst, src);
-  emit(imm8);
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x22, imm8);
 }
 
 void Assembler::pinsrd(XMMRegister dst, Operand src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x22);
-  emit_sse_operand(dst, src);
+  DCHECK(is_uint8(imm8));
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x22);
   emit(imm8);
 }
 
 void Assembler::pinsrb(XMMRegister dst, Register src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x20);
-  emit_sse_operand(dst, src);
-  emit(imm8);
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x20, imm8);
 }
 
 void Assembler::pinsrb(XMMRegister dst, Operand src, int8_t imm8) {
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x20);
-  emit_sse_operand(dst, src);
+  DCHECK(is_uint8(imm8));
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x20);
   emit(imm8);
 }
 
 void Assembler::insertps(XMMRegister dst, XMMRegister src, byte imm8) {
-  DCHECK(CpuFeatures::IsSupported(SSE4_1));
   DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x21);
-  emit_sse_operand(dst, src);
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x21);
   emit(imm8);
 }
 
 void Assembler::insertps(XMMRegister dst, Operand src, byte imm8) {
-  DCHECK(CpuFeatures::IsSupported(SSE4_1));
   DCHECK(is_uint8(imm8));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x21);
-  emit_sse_operand(dst, src);
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x21);
   emit(imm8);
 }
 
@@ -3758,28 +3628,14 @@ void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
 
 void Assembler::roundss(XMMRegister dst, XMMRegister src, RoundingMode mode) {
   DCHECK(!IsEnabled(AVX));
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x0A);
-  emit_sse_operand(dst, src);
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x0A);
   // Mask precision exception.
   emit(static_cast<byte>(mode) | 0x8);
 }
 
 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
   DCHECK(!IsEnabled(AVX));
-  DCHECK(IsEnabled(SSE4_1));
-  EnsureSpace ensure_space(this);
-  emit(0x66);
-  emit_optional_rex_32(dst, src);
-  emit(0x0F);
-  emit(0x3A);
-  emit(0x0B);
-  emit_sse_operand(dst, src);
+  sse4_instr(dst, src, 0x66, 0x0F, 0x3A, 0x0B);
   // Mask precision exception.
   emit(static_cast<byte>(mode) | 0x8);
 }
@@ -4441,6 +4297,21 @@ void Assembler::ssse3_instr(XMMRegister dst, Operand src, byte prefix,
   emit_sse_operand(dst, src);
 }
 
+void Assembler::sse4_instr(XMMRegister dst, Register src, byte prefix,
+                           byte escape1, byte escape2, byte opcode,
+                           int8_t imm8) {
+  DCHECK(is_uint8(imm8));
+  DCHECK(IsEnabled(SSE4_1));
+  EnsureSpace ensure_space(this);
+  emit(prefix);
+  emit_optional_rex_32(dst, src);
+  emit(escape1);
+  emit(escape2);
+  emit(opcode);
+  emit_sse_operand(dst, src);
+  emit(imm8);
+}
+
 void Assembler::sse4_instr(XMMRegister dst, XMMRegister src, byte prefix,
                            byte escape1, byte escape2, byte opcode) {
   DCHECK(IsEnabled(SSE4_1));
@@ -4465,6 +4336,36 @@ void Assembler::sse4_instr(XMMRegister dst, Operand src, byte prefix,
   emit_sse_operand(dst, src);
 }
 
+void Assembler::sse4_instr(Register dst, XMMRegister src, byte prefix,
+                           byte escape1, byte escape2, byte opcode,
+                           int8_t imm8) {
+  DCHECK(is_uint8(imm8));
+  DCHECK(IsEnabled(SSE4_1));
+  EnsureSpace ensure_space(this);
+  emit(prefix);
+  emit_optional_rex_32(src, dst);
+  emit(escape1);
+  emit(escape2);
+  emit(opcode);
+  emit_sse_operand(src, dst);
+  emit(imm8);
+}
+
+void Assembler::sse4_instr(Operand dst, XMMRegister src, byte prefix,
+                           byte escape1, byte escape2, byte opcode,
+                           int8_t imm8) {
+  DCHECK(is_uint8(imm8));
+  DCHECK(IsEnabled(SSE4_1));
+  EnsureSpace ensure_space(this);
+  emit(prefix);
+  emit_optional_rex_32(src, dst);
+  emit(escape1);
+  emit(escape2);
+  emit(opcode);
+  emit_sse_operand(src, dst);
+  emit(imm8);
+}
+
 void Assembler::sse4_2_instr(XMMRegister dst, XMMRegister src, byte prefix,
                              byte escape1, byte escape2, byte opcode) {
   DCHECK(IsEnabled(SSE4_2));

src/codegen/x64/assembler-x64.h

@@ -925,6 +925,12 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
 #undef DECLARE_SSSE3_INSTRUCTION
 
   // SSE4
+  void sse4_instr(Register dst, XMMRegister src, byte prefix, byte escape1,
+                  byte escape2, byte opcode, int8_t imm8);
+  void sse4_instr(Operand dst, XMMRegister src, byte prefix, byte escape1,
+                  byte escape2, byte opcode, int8_t imm8);
+  void sse4_instr(XMMRegister dst, Register src, byte prefix, byte escape1,
+                  byte escape2, byte opcode, int8_t imm8);
   void sse4_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
                   byte escape2, byte opcode);
   void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
@@ -941,6 +947,20 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
 #undef DECLARE_SSE4_INSTRUCTION
 
+#define DECLARE_SSE4_EXTRACT_INSTRUCTION(instruction, prefix, escape1,     \
+                                         escape2, opcode)                  \
+  void instruction(Register dst, XMMRegister src, int8_t imm8) {           \
+    sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
+               imm8);                                                      \
+  }                                                                        \
+  void instruction(Operand dst, XMMRegister src, int8_t imm8) {            \
+    sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
+               imm8);                                                      \
+  }
+
+  SSE4_EXTRACT_INSTRUCTION_LIST(DECLARE_SSE4_EXTRACT_INSTRUCTION)
+#undef DECLARE_SSE4_EXTRACT_INSTRUCTION
+
   // SSE4.2
   void sse4_2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
                     byte escape2, byte opcode);
@@ -1068,13 +1088,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   // SSE 4.1 instruction
   void insertps(XMMRegister dst, XMMRegister src, byte imm8);
   void insertps(XMMRegister dst, Operand src, byte imm8);
-  void extractps(Register dst, XMMRegister src, int8_t imm8);
-  void pextrb(Register dst, XMMRegister src, int8_t imm8);
-  void pextrb(Operand dst, XMMRegister src, int8_t imm8);
-  void pextrw(Register dst, XMMRegister src, int8_t imm8);
-  void pextrw(Operand dst, XMMRegister src, int8_t imm8);
-  void pextrd(Register dst, XMMRegister src, int8_t imm8);
-  void pextrd(Operand dst, XMMRegister src, int8_t imm8);
   void pextrq(Register dst, XMMRegister src, int8_t imm8);
   void pinsrb(XMMRegister dst, Register src, int8_t imm8);
   void pinsrb(XMMRegister dst, Operand src, int8_t imm8);

src/codegen/x64/sse-instr.h

@@ -118,6 +118,12 @@
   V(pmaxud, 66, 0F, 38, 3F)      \
   V(pmulld, 66, 0F, 38, 40)
 
+#define SSE4_EXTRACT_INSTRUCTION_LIST(V) \
+  V(extractps, 66, 0F, 3A, 17)           \
+  V(pextrb, 66, 0F, 3A, 14)              \
+  V(pextrw, 66, 0F, 3A, 15)              \
+  V(pextrd, 66, 0F, 3A, 16)
+
 #define SSE4_2_INSTRUCTION_LIST(V) V(pcmpgtq, 66, 0F, 38, 37)
 
 #endif  // V8_CODEGEN_X64_SSE_INSTR_H_

test/cctest/test-disasm-x64.cc

@@ -505,6 +505,11 @@ TEST(DisasmX64) {
   __ instruction(xmm5, xmm1);                                                 \
   __ instruction(xmm5, Operand(rdx, 4));
 
+#define EMIT_SSE34_IMM_INSTR(instruction, notUsed1, notUsed2, notUsed3, \
+                             notUsed4)                                  \
+  __ instruction(rbx, xmm15, 0);                                        \
+  __ instruction(Operand(rax, 10), xmm0, 1);
+
   {
     if (CpuFeatures::IsSupported(SSSE3)) {
       CpuFeatureScope scope(&assm, SSSE3);
@@ -518,11 +523,7 @@ TEST(DisasmX64) {
     if (CpuFeatures::IsSupported(SSE4_1)) {
       CpuFeatureScope scope(&assm, SSE4_1);
       __ insertps(xmm5, xmm1, 123);
-      __ extractps(rax, xmm1, 0);
-      __ pextrw(rbx, xmm2, 1);
       __ pinsrw(xmm2, rcx, 1);
-      __ pextrd(rbx, xmm15, 0);
-      __ pextrd(r12, xmm0, 1);
       __ pextrq(r12, xmm0, 1);
       __ pinsrd(xmm9, r9, 0);
       __ pinsrd(xmm5, Operand(rax, 4), 1);
@@ -582,6 +583,7 @@ TEST(DisasmX64) {
       __ cvtdq2ps(xmm5, Operand(rdx, 4));
 
       SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
+      SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR)
     }
   }
 
@@ -593,6 +595,7 @@ TEST(DisasmX64) {
     }
   }
 #undef EMIT_SSE34_INSTR
+#undef EMIT_SSE34_IMM_INSTR
 
   // AVX instruction
   {