PPC: Fix "[turbofan] Add support for reinterpreting integers as floating point and vice versa."

R=titzer@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, dstence@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1358193002

Cr-Commit-Position: refs/heads/master@{#30870}

src/compiler/ppc/code-generator-ppc.cc

@@ -1076,12 +1076,18 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
 #endif
       DCHECK_EQ(LeaveRC, i.OutputRCBit());
       break;
+    case kPPC_BitcastFloat32ToInt32:
+      __ MovFloatToInt(i.OutputRegister(), i.InputDoubleRegister(0));
+      break;
+    case kPPC_BitcastInt32ToFloat32:
+      __ MovIntToFloat(i.OutputDoubleRegister(), i.InputRegister(0));
+      break;
 #if V8_TARGET_ARCH_PPC64
-    case kPPC_BitcastDL:
-      __ mffprd(i.OutputRegister(), i.InputDoubleRegister(0));
+    case kPPC_BitcastDoubleToInt64:
+      __ MovDoubleToInt64(i.OutputRegister(), i.InputDoubleRegister(0));
       break;
-    case kPPC_BitcastLD:
-      __ mtfprd(i.OutputDoubleRegister(), i.InputRegister(0));
+    case kPPC_BitcastInt64ToDouble:
+      __ MovInt64ToDouble(i.OutputDoubleRegister(), i.InputRegister(0));
       break;
 #endif
     case kPPC_LoadWordU8:

src/compiler/ppc/instruction-codes-ppc.h

@@ -86,8 +86,10 @@ namespace compiler {
   V(PPC_DoubleInsertLowWord32)     \
   V(PPC_DoubleInsertHighWord32)    \
   V(PPC_DoubleConstruct)           \
-  V(PPC_BitcastDL)                 \
-  V(PPC_BitcastLD)                 \
+  V(PPC_BitcastInt32ToFloat32)     \
+  V(PPC_BitcastFloat32ToInt32)     \
+  V(PPC_BitcastInt64ToDouble)      \
+  V(PPC_BitcastDoubleToInt64)      \
   V(PPC_LoadWordS8)                \
   V(PPC_LoadWordU8)                \
   V(PPC_LoadWordS16)               \

src/compiler/ppc/instruction-selector-ppc.cc

@@ -911,28 +911,25 @@ void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
 
 
 void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
-  VisitRR(this, kPPC_DoubleExtractLowWord32, node);
+  VisitRR(this, kPPC_BitcastFloat32ToInt32, node);
 }
 
 
 #if V8_TARGET_ARCH_PPC64
 void InstructionSelector::VisitBitcastFloat64ToInt64(Node* node) {
-  VisitRR(this, kPPC_BitcastDL, node);
+  VisitRR(this, kPPC_BitcastDoubleToInt64, node);
 }
 #endif
 
 
 void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) {
-  PPCOperandGenerator g(this);
-  Emit(kPPC_DoubleInsertLowWord32, g.DefineAsRegister(node),
-       ImmediateOperand(ImmediateOperand::INLINE, 0),
-       g.UseRegister(node->InputAt(0)));
+  VisitRR(this, kPPC_BitcastInt32ToFloat32, node);
 }
 
 
 #if V8_TARGET_ARCH_PPC64
 void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) {
-  VisitRR(this, kPPC_BitcastLD, node);
+  VisitRR(this, kPPC_BitcastInt64ToDouble, node);
 }
 #endif
 

src/ppc/macro-assembler-ppc.cc

@@ -3749,6 +3749,25 @@ void MacroAssembler::MovDoubleToInt64(
 }
 
 
+void MacroAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
+  subi(sp, sp, Operand(kFloatSize));
+  stw(src, MemOperand(sp, 0));
+  nop(GROUP_ENDING_NOP);  // LHS/RAW optimization
+  lfs(dst, MemOperand(sp, 0));
+  addi(sp, sp, Operand(kFloatSize));
+}
+
+
+void MacroAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
+  subi(sp, sp, Operand(kFloatSize));
+  frsp(src, src);
+  stfs(src, MemOperand(sp, 0));
+  nop(GROUP_ENDING_NOP);  // LHS/RAW optimization
+  lwz(dst, MemOperand(sp, 0));
+  addi(sp, sp, Operand(kFloatSize));
+}
+
+
 void MacroAssembler::Add(Register dst, Register src, intptr_t value,
                          Register scratch) {
   if (is_int16(value)) {

src/ppc/macro-assembler-ppc.h

@@ -497,6 +497,8 @@ class MacroAssembler : public Assembler {
       Register dst_hi,
 #endif
       Register dst, DoubleRegister src);
+  void MovIntToFloat(DoubleRegister dst, Register src);
+  void MovFloatToInt(Register dst, DoubleRegister src);
 
   void Add(Register dst, Register src, intptr_t value, Register scratch);
   void Cmpi(Register src1, const Operand& src2, Register scratch,