[wasm-simd][x64] Add AVX codegen

For a bunch of s8x16, s16x2 and s32x4 shuffle ops (generated by
s8x16shuffle).

Bug: v8:9561
Change-Id: I0e5cd8a90edba8bc15918c0ca1dc830475db2769
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2110952Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66865}

src/codegen/x64/assembler-x64.h

@@ -1523,6 +1523,10 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
     emit(imm8);
   }
+  void vpshufd(XMMRegister dst, Operand src, uint8_t imm8) {
+    vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
+    emit(imm8);
+  }
   void vpshuflw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
     vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
     emit(imm8);
@@ -1531,6 +1535,14 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
     emit(imm8);
   }
+  void vpshufhw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
+    vinstr(0x70, dst, xmm0, src, kF3, k0F, kWIG);
+    emit(imm8);
+  }
+  void vpshufhw(XMMRegister dst, Operand src, uint8_t imm8) {
+    vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
+    emit(imm8);
+  }
 
   void vpblendw(XMMRegister dst, XMMRegister src1, XMMRegister src2,
                 uint8_t mask) {

src/codegen/x64/macro-assembler-x64.h

@@ -216,10 +216,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   AVX_OP(Mulps, mulps)
   AVX_OP(Divps, divps)
   AVX_OP(Pshuflw, pshuflw)
+  AVX_OP(Pshufhw, pshufhw)
   AVX_OP(Packsswb, packsswb)
   AVX_OP(Packuswb, packuswb)
   AVX_OP(Packssdw, packssdw)
+  AVX_OP(Punpcklbw, punpcklbw)
+  AVX_OP(Punpcklwd, punpcklwd)
+  AVX_OP(Punpckldq, punpckldq)
+  AVX_OP(Punpckhbw, punpckhbw)
+  AVX_OP(Punpckhwd, punpckhwd)
+  AVX_OP(Punpckhdq, punpckhdq)
   AVX_OP(Punpcklqdq, punpcklqdq)
+  AVX_OP(Punpckhqdq, punpckhqdq)
   AVX_OP(Pshufd, pshufd)
   AVX_OP(Cmpps, cmpps)
   AVX_OP(Cmppd, cmppd)

src/compiler/backend/code-generator-impl.h

@@ -62,6 +62,10 @@ class InstructionOperandConverter {
     return static_cast<int8_t>(InputInt32(index));
   }
 
+  uint8_t InputUint8(size_t index) {
+    return bit_cast<uint8_t>(InputInt8(index));
+  }
+
   int16_t InputInt16(size_t index) {
     return static_cast<int16_t>(InputInt32(index));
   }

src/diagnostics/x64/disasm-x64.cc

@@ -1096,6 +1096,11 @@ int DisassemblerX64::AVXInstruction(byte* data) {
         AppendToBuffer("vmovdqu %s,", NameOfXMMRegister(regop));
         current += PrintRightXMMOperand(current);
         break;
+      case 0x70:
+        AppendToBuffer("vpshufhw %s,", NameOfXMMRegister(regop));
+        current += PrintRightXMMOperand(current);
+        AppendToBuffer(",0x%x", *current++);
+        break;
       case 0x7F:
         AppendToBuffer("vmovdqu ");
         current += PrintRightXMMOperand(current);

test/cctest/test-disasm-x64.cc

@@ -783,8 +783,11 @@ TEST(DisasmX64) {
       __ vpinsrq(xmm1, xmm2, rax, 9);
       __ vpinsrq(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 9);
       __ vpshufd(xmm1, xmm2, 85);
+      __ vpshufd(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
       __ vpshuflw(xmm1, xmm2, 85);
       __ vpshuflw(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
+      __ vpshufhw(xmm1, xmm2, 85);
+      __ vpshufhw(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
       __ vshufps(xmm3, xmm2, xmm3, 3);
       __ vpblendw(xmm1, xmm2, xmm3, 23);
       __ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23);