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Commit 2e8ac7bb authored by jing.bao's avatar jing.bao Committed by Commit Bot
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[ia32][wasm] Add I16x8 CompareOp, I16x8Neg and I8x16Neg. 

I16x8 GtS/GeS/GtU/GeU
I16x8Neg, I8x16Neg
Add Psignb, Psignw, Psubb, Psubw macros

Bug: 
Change-Id: Id38f15140727051e185054295722282b77ea889c
Reviewed-on: https://chromium-review.googlesource.com/773831
Commit-Queue: Jing Bao <jing.bao@intel.com>
Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49610}
parent f5a5a778
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Showing with 204 additions and 33 deletions
src/compiler/ia32/code-generator-ia32.cc
View file @ 2e8ac7bb
...@@ -2016,6 +2016,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2016,6 +2016,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4ReplaceLane: { case kSSEI32x4ReplaceLane: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pinsrd(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1)); __ pinsrd(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1));
break; break;
...@@ -2029,8 +2030,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2029,8 +2030,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kIA32I32x4Neg: { case kIA32I32x4Neg: {
XMMRegister dst = i.OutputSimd128Register(); XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0); Operand src = i.InputOperand(0);
Register ireg = Register::from_code(dst.code()); if (src.is_reg(dst)) {
if (src.is_reg(ireg)) {
__ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg); __ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ Psignd(dst, kScratchDoubleReg); __ Psignd(dst, kScratchDoubleReg);
} else { } else {
...@@ -2040,6 +2040,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2040,6 +2040,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4Shl: { case kSSEI32x4Shl: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pslld(i.OutputSimd128Register(), i.InputInt8(1)); __ pslld(i.OutputSimd128Register(), i.InputInt8(1));
break; break;
} }
...@@ -2050,6 +2051,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2050,6 +2051,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4ShrS: { case kSSEI32x4ShrS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psrad(i.OutputSimd128Register(), i.InputInt8(1)); __ psrad(i.OutputSimd128Register(), i.InputInt8(1));
break; break;
} }
...@@ -2060,6 +2062,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2060,6 +2062,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4Add: { case kSSEI32x4Add: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ paddd(i.OutputSimd128Register(), i.InputOperand(1)); __ paddd(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2070,6 +2073,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2070,6 +2073,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4Sub: { case kSSEI32x4Sub: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psubd(i.OutputSimd128Register(), i.InputOperand(1)); __ psubd(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2080,6 +2084,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2080,6 +2084,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4Mul: { case kSSEI32x4Mul: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pmulld(i.OutputSimd128Register(), i.InputOperand(1)); __ pmulld(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2091,6 +2096,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2091,6 +2096,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4MinS: { case kSSEI32x4MinS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pminsd(i.OutputSimd128Register(), i.InputOperand(1)); __ pminsd(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2102,6 +2108,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2102,6 +2108,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4MaxS: { case kSSEI32x4MaxS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pmaxsd(i.OutputSimd128Register(), i.InputOperand(1)); __ pmaxsd(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2113,6 +2120,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2113,6 +2120,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4Eq: { case kSSEI32x4Eq: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pcmpeqd(i.OutputSimd128Register(), i.InputOperand(1)); __ pcmpeqd(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2123,6 +2131,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2123,6 +2131,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4Ne: { case kSSEI32x4Ne: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pcmpeqd(i.OutputSimd128Register(), i.InputOperand(1)); __ pcmpeqd(i.OutputSimd128Register(), i.InputOperand(1));
__ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg); __ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(i.OutputSimd128Register(), kScratchDoubleReg); __ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
...@@ -2138,6 +2147,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2138,6 +2147,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4GtS: { case kSSEI32x4GtS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pcmpgtd(i.OutputSimd128Register(), i.InputOperand(1)); __ pcmpgtd(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2148,6 +2158,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2148,6 +2158,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4GeS: { case kSSEI32x4GeS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register(); XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(1); Operand src = i.InputOperand(1);
...@@ -2164,6 +2175,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2164,6 +2175,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4ShrU: { case kSSEI32x4ShrU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psrld(i.OutputSimd128Register(), i.InputInt8(1)); __ psrld(i.OutputSimd128Register(), i.InputInt8(1));
break; break;
} }
...@@ -2174,6 +2186,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2174,6 +2186,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4MinU: { case kSSEI32x4MinU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pminud(i.OutputSimd128Register(), i.InputOperand(1)); __ pminud(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2185,6 +2198,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2185,6 +2198,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4MaxU: { case kSSEI32x4MaxU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pmaxud(i.OutputSimd128Register(), i.InputOperand(1)); __ pmaxud(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2196,6 +2210,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2196,6 +2210,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4GtU: { case kSSEI32x4GtU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register(); XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(1); Operand src = i.InputOperand(1);
...@@ -2217,6 +2232,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2217,6 +2232,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI32x4GeU: { case kSSEI32x4GeU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register(); XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(1); Operand src = i.InputOperand(1);
...@@ -2246,6 +2262,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2246,6 +2262,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8ReplaceLane: { case kSSEI16x8ReplaceLane: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pinsrw(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1)); __ pinsrw(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1));
break; break;
} }
...@@ -2255,7 +2272,20 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2255,7 +2272,20 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(2), i.InputInt8(1)); i.InputOperand(2), i.InputInt8(1));
break; break;
} }
case kIA32I16x8Neg: {
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0);
if (src.is_reg(dst)) {
__ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ Psignw(dst, kScratchDoubleReg);
} else {
__ Pxor(dst, dst);
__ Psubw(dst, src);
}
break;
}
case kSSEI16x8Shl: { case kSSEI16x8Shl: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psllw(i.OutputSimd128Register(), i.InputInt8(1)); __ psllw(i.OutputSimd128Register(), i.InputInt8(1));
break; break;
} }
...@@ -2266,6 +2296,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2266,6 +2296,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8ShrS: { case kSSEI16x8ShrS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psraw(i.OutputSimd128Register(), i.InputInt8(1)); __ psraw(i.OutputSimd128Register(), i.InputInt8(1));
break; break;
} }
...@@ -2276,6 +2307,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2276,6 +2307,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8Add: { case kSSEI16x8Add: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ paddw(i.OutputSimd128Register(), i.InputOperand(1)); __ paddw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2286,6 +2318,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2286,6 +2318,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8AddSaturateS: { case kSSEI16x8AddSaturateS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ paddsw(i.OutputSimd128Register(), i.InputOperand(1)); __ paddsw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2296,6 +2329,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2296,6 +2329,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8Sub: { case kSSEI16x8Sub: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psubw(i.OutputSimd128Register(), i.InputOperand(1)); __ psubw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2306,6 +2340,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2306,6 +2340,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8SubSaturateS: { case kSSEI16x8SubSaturateS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psubsw(i.OutputSimd128Register(), i.InputOperand(1)); __ psubsw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2316,6 +2351,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2316,6 +2351,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8Mul: { case kSSEI16x8Mul: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pmullw(i.OutputSimd128Register(), i.InputOperand(1)); __ pmullw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2326,6 +2362,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2326,6 +2362,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8MinS: { case kSSEI16x8MinS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pminsw(i.OutputSimd128Register(), i.InputOperand(1)); __ pminsw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2336,6 +2373,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2336,6 +2373,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8MaxS: { case kSSEI16x8MaxS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pmaxsw(i.OutputSimd128Register(), i.InputOperand(1)); __ pmaxsw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2346,6 +2384,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2346,6 +2384,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8Eq: { case kSSEI16x8Eq: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pcmpeqw(i.OutputSimd128Register(), i.InputOperand(1)); __ pcmpeqw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2356,6 +2395,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2356,6 +2395,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8Ne: { case kSSEI16x8Ne: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pcmpeqw(i.OutputSimd128Register(), i.InputOperand(1)); __ pcmpeqw(i.OutputSimd128Register(), i.InputOperand(1));
__ pcmpeqw(kScratchDoubleReg, kScratchDoubleReg); __ pcmpeqw(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(i.OutputSimd128Register(), kScratchDoubleReg); __ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
...@@ -2370,7 +2410,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2370,7 +2410,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kScratchDoubleReg); kScratchDoubleReg);
break; break;
} }
case kSSEI16x8GtS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ pcmpgtw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8GtS: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpcmpgtw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8GeS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(1);
__ pminsw(dst, src);
__ pcmpeqw(dst, src);
break;
}
case kAVXI16x8GeS: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister src1 = i.InputSimd128Register(0);
Operand src2 = i.InputOperand(1);
__ vpminsw(kScratchDoubleReg, src1, src2);
__ vpcmpeqw(i.OutputSimd128Register(), kScratchDoubleReg, src2);
break;
}
case kSSEI16x8ShrU: { case kSSEI16x8ShrU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psrlw(i.OutputSimd128Register(), i.InputInt8(1)); __ psrlw(i.OutputSimd128Register(), i.InputInt8(1));
break; break;
} }
...@@ -2381,6 +2449,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2381,6 +2449,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8AddSaturateU: { case kSSEI16x8AddSaturateU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ paddusw(i.OutputSimd128Register(), i.InputOperand(1)); __ paddusw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2391,6 +2460,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2391,6 +2460,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8SubSaturateU: { case kSSEI16x8SubSaturateU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psubusw(i.OutputSimd128Register(), i.InputOperand(1)); __ psubusw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
} }
...@@ -2401,6 +2471,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2401,6 +2471,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8MinU: { case kSSEI16x8MinU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pminuw(i.OutputSimd128Register(), i.InputOperand(1)); __ pminuw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2412,6 +2483,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2412,6 +2483,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI16x8MaxU: { case kSSEI16x8MaxU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pmaxuw(i.OutputSimd128Register(), i.InputOperand(1)); __ pmaxuw(i.OutputSimd128Register(), i.InputOperand(1));
break; break;
...@@ -2422,6 +2494,45 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2422,6 +2494,45 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(1)); i.InputOperand(1));
break; break;
} }
case kSSEI16x8GtU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(1);
__ pmaxuw(dst, src);
__ pcmpeqw(dst, src);
__ pcmpeqw(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(dst, kScratchDoubleReg);
break;
}
case kAVXI16x8GtU: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src1 = i.InputSimd128Register(0);
Operand src2 = i.InputOperand(1);
__ vpmaxuw(kScratchDoubleReg, src1, src2);
__ vpcmpeqw(dst, kScratchDoubleReg, src2);
__ vpcmpeqw(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ vpxor(dst, dst, kScratchDoubleReg);
break;
}
case kSSEI16x8GeU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(1);
__ pminuw(dst, src);
__ pcmpeqw(dst, src);
break;
}
case kAVXI16x8GeU: {
CpuFeatureScope avx_scope(tasm(), AVX);
XMMRegister src1 = i.InputSimd128Register(0);
Operand src2 = i.InputOperand(1);
__ vpminuw(kScratchDoubleReg, src1, src2);
__ vpcmpeqw(i.OutputSimd128Register(), kScratchDoubleReg, src2);
break;
}
case kIA32I8x16Splat: { case kIA32I8x16Splat: {
XMMRegister dst = i.OutputSimd128Register(); XMMRegister dst = i.OutputSimd128Register();
__ Movd(dst, i.InputOperand(0)); __ Movd(dst, i.InputOperand(0));
...@@ -2436,6 +2547,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2436,6 +2547,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kSSEI8x16ReplaceLane: { case kSSEI8x16ReplaceLane: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1); CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pinsrb(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1)); __ pinsrb(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1));
break; break;
...@@ -2446,6 +2558,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2446,6 +2558,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(2), i.InputInt8(1)); i.InputOperand(2), i.InputInt8(1));
break; break;
} }
case kIA32I8x16Neg: {
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0);
if (src.is_reg(dst)) {
__ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ Psignb(dst, kScratchDoubleReg);
} else {
__ Pxor(dst, dst);
__ Psubb(dst, src);
}
break;
}
case kCheckedLoadInt8: case kCheckedLoadInt8:
ASSEMBLE_CHECKED_LOAD_INTEGER(movsx_b); ASSEMBLE_CHECKED_LOAD_INTEGER(movsx_b);
break; break;
......
src/compiler/ia32/instruction-codes-ia32.h
View file @ 2e8ac7bb
...@@ -152,6 +152,7 @@ namespace compiler { ...@@ -152,6 +152,7 @@ namespace compiler {
V(IA32I16x8ExtractLane) \ V(IA32I16x8ExtractLane) \
V(SSEI16x8ReplaceLane) \ V(SSEI16x8ReplaceLane) \
V(AVXI16x8ReplaceLane) \ V(AVXI16x8ReplaceLane) \
V(IA32I16x8Neg) \
V(SSEI16x8Shl) \ V(SSEI16x8Shl) \
V(AVXI16x8Shl) \ V(AVXI16x8Shl) \
V(SSEI16x8ShrS) \ V(SSEI16x8ShrS) \
...@@ -174,6 +175,10 @@ namespace compiler { ...@@ -174,6 +175,10 @@ namespace compiler {
V(AVXI16x8Eq) \ V(AVXI16x8Eq) \
V(SSEI16x8Ne) \ V(SSEI16x8Ne) \
V(AVXI16x8Ne) \ V(AVXI16x8Ne) \
V(SSEI16x8GtS) \
V(AVXI16x8GtS) \
V(SSEI16x8GeS) \
V(AVXI16x8GeS) \
V(SSEI16x8ShrU) \ V(SSEI16x8ShrU) \
V(AVXI16x8ShrU) \ V(AVXI16x8ShrU) \
V(SSEI16x8AddSaturateU) \ V(SSEI16x8AddSaturateU) \
...@@ -184,10 +189,15 @@ namespace compiler { ...@@ -184,10 +189,15 @@ namespace compiler {
V(AVXI16x8MinU) \ V(AVXI16x8MinU) \
V(SSEI16x8MaxU) \ V(SSEI16x8MaxU) \
V(AVXI16x8MaxU) \ V(AVXI16x8MaxU) \
V(SSEI16x8GtU) \
V(AVXI16x8GtU) \
V(SSEI16x8GeU) \
V(AVXI16x8GeU) \
V(IA32I8x16Splat) \ V(IA32I8x16Splat) \
V(IA32I8x16ExtractLane) \ V(IA32I8x16ExtractLane) \
V(SSEI8x16ReplaceLane) \ V(SSEI8x16ReplaceLane) \
V(AVXI8x16ReplaceLane) V(AVXI8x16ReplaceLane) \
V(IA32I8x16Neg)
// Addressing modes represent the "shape" of inputs to an instruction. // Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes // Many instructions support multiple addressing modes. Addressing modes
......
src/compiler/ia32/instruction-scheduler-ia32.cc
View file @ 2e8ac7bb
...@@ -138,6 +138,7 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -138,6 +138,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kIA32I16x8ExtractLane: case kIA32I16x8ExtractLane:
case kSSEI16x8ReplaceLane: case kSSEI16x8ReplaceLane:
case kAVXI16x8ReplaceLane: case kAVXI16x8ReplaceLane:
case kIA32I16x8Neg:
case kSSEI16x8Shl: case kSSEI16x8Shl:
case kAVXI16x8Shl: case kAVXI16x8Shl:
case kSSEI16x8ShrS: case kSSEI16x8ShrS:
...@@ -160,6 +161,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -160,6 +161,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXI16x8Eq: case kAVXI16x8Eq:
case kSSEI16x8Ne: case kSSEI16x8Ne:
case kAVXI16x8Ne: case kAVXI16x8Ne:
case kSSEI16x8GtS:
case kAVXI16x8GtS:
case kSSEI16x8GeS:
case kAVXI16x8GeS:
case kSSEI16x8ShrU: case kSSEI16x8ShrU:
case kAVXI16x8ShrU: case kAVXI16x8ShrU:
case kSSEI16x8AddSaturateU: case kSSEI16x8AddSaturateU:
...@@ -170,10 +175,15 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -170,10 +175,15 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXI16x8MinU: case kAVXI16x8MinU:
case kSSEI16x8MaxU: case kSSEI16x8MaxU:
case kAVXI16x8MaxU: case kAVXI16x8MaxU:
case kSSEI16x8GtU:
case kAVXI16x8GtU:
case kSSEI16x8GeU:
case kAVXI16x8GeU:
case kIA32I8x16Splat: case kIA32I8x16Splat:
case kIA32I8x16ExtractLane: case kIA32I8x16ExtractLane:
case kSSEI8x16ReplaceLane: case kSSEI8x16ReplaceLane:
case kAVXI8x16ReplaceLane: case kAVXI8x16ReplaceLane:
case kIA32I8x16Neg:
return (instr->addressing_mode() == kMode_None) return (instr->addressing_mode() == kMode_None)
? kNoOpcodeFlags ? kNoOpcodeFlags
: kIsLoadOperation | kHasSideEffect; : kIsLoadOperation | kHasSideEffect;
......
src/compiler/ia32/instruction-selector-ia32.cc
View file @ 2e8ac7bb
...@@ -1925,12 +1925,19 @@ VISIT_ATOMIC_BINOP(Xor) ...@@ -1925,12 +1925,19 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8MaxS) \ V(I16x8MaxS) \
V(I16x8Eq) \ V(I16x8Eq) \
V(I16x8Ne) \ V(I16x8Ne) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8AddSaturateU) \ V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \ V(I16x8SubSaturateU) \
V(I16x8MinU) \ V(I16x8MinU) \
V(I16x8MaxU) V(I16x8MaxU) \
V(I16x8GtU) \
#define SIMD_UNOP_LIST(V) V(I32x4Neg) V(I16x8GeU)
#define SIMD_UNOP_LIST(V) \
V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg)
#define SIMD_SHIFT_OPCODES(V) \ #define SIMD_SHIFT_OPCODES(V) \
V(I32x4Shl) \ V(I32x4Shl) \
......
src/compiler/instruction-selector.cc
View file @ 2e8ac7bb
...@@ -2283,15 +2283,11 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) { ...@@ -2283,15 +2283,11 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
void InstructionSelector::VisitI16x8MinU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MaxU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8MaxU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 #endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64 // && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \ #if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64 !V8_TARGET_ARCH_MIPS64
...@@ -2310,7 +2306,7 @@ void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) { ...@@ -2310,7 +2306,7 @@ void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
// && !V8_TARGET_ARCH_MIPS64 // && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \ #if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64 !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8GeS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8GeS(Node* node) { UNIMPLEMENTED(); }
...@@ -2321,7 +2317,8 @@ void InstructionSelector::VisitI16x8GeU(Node* node) { UNIMPLEMENTED(); } ...@@ -2321,7 +2317,8 @@ void InstructionSelector::VisitI16x8GeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 #endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64 // && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \ #if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64 !V8_TARGET_ARCH_MIPS64
......
src/ia32/assembler-ia32.cc
View file @ 2e8ac7bb
...@@ -295,12 +295,6 @@ Operand::Operand(Register index, ...@@ -295,12 +295,6 @@ Operand::Operand(Register index,
} }
bool Operand::is_reg(Register reg) const {
return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
&& ((buf_[0] & 0x07) == reg.code()); // register codes match.
}
bool Operand::is_reg_only() const { bool Operand::is_reg_only() const {
return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only. return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
} }
......
src/ia32/assembler-ia32.h
View file @ 2e8ac7bb
...@@ -392,7 +392,8 @@ class Operand BASE_EMBEDDED { ...@@ -392,7 +392,8 @@ class Operand BASE_EMBEDDED {
} }
// Returns true if this Operand is a wrapper for the specified register. // Returns true if this Operand is a wrapper for the specified register.
bool is_reg(Register reg) const; bool is_reg(Register reg) const { return is_reg(reg.code()); }
bool is_reg(XMMRegister reg) const { return is_reg(reg.code()); }
// Returns true if this Operand is a wrapper for one register. // Returns true if this Operand is a wrapper for one register.
bool is_reg_only() const; bool is_reg_only() const;
...@@ -420,6 +421,11 @@ class Operand BASE_EMBEDDED { ...@@ -420,6 +421,11 @@ class Operand BASE_EMBEDDED {
rmode_ = rmode; rmode_ = rmode;
} }
inline bool is_reg(int reg_code) const {
return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
&& ((buf_[0] & 0x07) == reg_code); // register codes match.
}
byte buf_[6]; byte buf_[6];
// The number of bytes in buf_. // The number of bytes in buf_.
unsigned int len_; unsigned int len_;
......
src/ia32/macro-assembler-ia32.cc
View file @ 2e8ac7bb
...@@ -1253,6 +1253,34 @@ void TurboAssembler::Pshufd(XMMRegister dst, const Operand& src, ...@@ -1253,6 +1253,34 @@ void TurboAssembler::Pshufd(XMMRegister dst, const Operand& src,
} }
} }
void TurboAssembler::Psignb(XMMRegister dst, const Operand& src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignb(dst, dst, src);
return;
}
if (CpuFeatures::IsSupported(SSSE3)) {
CpuFeatureScope sse_scope(this, SSSE3);
psignb(dst, src);
return;
}
UNREACHABLE();
}
void TurboAssembler::Psignw(XMMRegister dst, const Operand& src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignw(dst, dst, src);
return;
}
if (CpuFeatures::IsSupported(SSSE3)) {
CpuFeatureScope sse_scope(this, SSSE3);
psignw(dst, src);
return;
}
UNREACHABLE();
}
void TurboAssembler::Psignd(XMMRegister dst, const Operand& src) { void TurboAssembler::Psignd(XMMRegister dst, const Operand& src) {
if (CpuFeatures::IsSupported(AVX)) { if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX); CpuFeatureScope scope(this, AVX);
......
src/ia32/macro-assembler-ia32.h
View file @ 2e8ac7bb
...@@ -237,6 +237,8 @@ class TurboAssembler : public Assembler { ...@@ -237,6 +237,8 @@ class TurboAssembler : public Assembler {
AVX_OP3_WITH_TYPE(macro_name, name, XMMRegister, const Operand&) AVX_OP3_WITH_TYPE(macro_name, name, XMMRegister, const Operand&)
AVX_OP3_XO(Pcmpeqd, pcmpeqd) AVX_OP3_XO(Pcmpeqd, pcmpeqd)
AVX_OP3_XO(Psubb, psubb)
AVX_OP3_XO(Psubw, psubw)
AVX_OP3_XO(Psubd, psubd) AVX_OP3_XO(Psubd, psubd)
AVX_OP3_XO(Pxor, pxor) AVX_OP3_XO(Pxor, pxor)
...@@ -246,6 +248,11 @@ class TurboAssembler : public Assembler { ...@@ -246,6 +248,11 @@ class TurboAssembler : public Assembler {
// Non-SSE2 instructions. // Non-SSE2 instructions.
void Pshufb(XMMRegister dst, XMMRegister src) { Pshufb(dst, Operand(src)); } void Pshufb(XMMRegister dst, XMMRegister src) { Pshufb(dst, Operand(src)); }
void Pshufb(XMMRegister dst, const Operand& src); void Pshufb(XMMRegister dst, const Operand& src);
void Psignb(XMMRegister dst, XMMRegister src) { Psignb(dst, Operand(src)); }
void Psignb(XMMRegister dst, const Operand& src);
void Psignw(XMMRegister dst, XMMRegister src) { Psignw(dst, Operand(src)); }
void Psignw(XMMRegister dst, const Operand& src);
void Psignd(XMMRegister dst, XMMRegister src) { Psignd(dst, Operand(src)); } void Psignd(XMMRegister dst, XMMRegister src) { Psignd(dst, Operand(src)); }
void Psignd(XMMRegister dst, const Operand& src); void Psignd(XMMRegister dst, const Operand& src);
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ 2e8ac7bb
...@@ -1113,8 +1113,6 @@ WASM_SIMD_COMPILED_TEST(I16x8ConvertI8x16) { ...@@ -1113,8 +1113,6 @@ WASM_SIMD_COMPILED_TEST(I16x8ConvertI8x16) {
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || #endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64 // V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_X64
void RunI16x8UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op, void RunI16x8UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op,
Int16UnOp expected_op) { Int16UnOp expected_op) {
WasmRunner<int32_t, int32_t, int32_t> r(execution_mode); WasmRunner<int32_t, int32_t, int32_t> r(execution_mode);
...@@ -1131,8 +1129,6 @@ void RunI16x8UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op, ...@@ -1131,8 +1129,6 @@ void RunI16x8UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op,
WASM_SIMD_TEST(I16x8Neg) { WASM_SIMD_TEST(I16x8Neg) {
RunI16x8UnOpTest(execution_mode, kExprI16x8Neg, Negate); RunI16x8UnOpTest(execution_mode, kExprI16x8Neg, Negate);
} }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \ #if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 V8_TARGET_ARCH_MIPS64
...@@ -1258,8 +1254,6 @@ WASM_SIMD_TEST(I16x8Ne) { ...@@ -1258,8 +1254,6 @@ WASM_SIMD_TEST(I16x8Ne) {
RunI16x8CompareOpTest(execution_mode, kExprI16x8Ne, NotEqual); RunI16x8CompareOpTest(execution_mode, kExprI16x8Ne, NotEqual);
} }
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST(I16x8LtS) { WASM_SIMD_TEST(I16x8LtS) {
RunI16x8CompareOpTest(execution_mode, kExprI16x8LtS, Less); RunI16x8CompareOpTest(execution_mode, kExprI16x8LtS, Less);
} }
...@@ -1291,8 +1285,6 @@ WASM_SIMD_TEST(I16x8LtU) { ...@@ -1291,8 +1285,6 @@ WASM_SIMD_TEST(I16x8LtU) {
WASM_SIMD_TEST(I16x8LeU) { WASM_SIMD_TEST(I16x8LeU) {
RunI16x8CompareOpTest(execution_mode, kExprI16x8LeU, UnsignedLessEqual); RunI16x8CompareOpTest(execution_mode, kExprI16x8LeU, UnsignedLessEqual);
} }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
void RunI16x8ShiftOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op, void RunI16x8ShiftOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op,
Int16ShiftOp expected_op, int shift) { Int16ShiftOp expected_op, int shift) {
...@@ -1320,8 +1312,6 @@ WASM_SIMD_TEST(I16x8ShrU) { ...@@ -1320,8 +1312,6 @@ WASM_SIMD_TEST(I16x8ShrU) {
RunI16x8ShiftOpTest(execution_mode, kExprI16x8ShrU, LogicalShiftRight, 1); RunI16x8ShiftOpTest(execution_mode, kExprI16x8ShrU, LogicalShiftRight, 1);
} }
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
void RunI8x16UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op, void RunI8x16UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op,
Int8UnOp expected_op) { Int8UnOp expected_op) {
WasmRunner<int32_t, int32_t, int32_t> r(execution_mode); WasmRunner<int32_t, int32_t, int32_t> r(execution_mode);
...@@ -1338,8 +1328,6 @@ void RunI8x16UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op, ...@@ -1338,8 +1328,6 @@ void RunI8x16UnOpTest(WasmExecutionMode execution_mode, WasmOpcode simd_op,
WASM_SIMD_TEST(I8x16Neg) { WASM_SIMD_TEST(I8x16Neg) {
RunI8x16UnOpTest(execution_mode, kExprI8x16Neg, Negate); RunI8x16UnOpTest(execution_mode, kExprI8x16Neg, Negate);
} }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \ #if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 V8_TARGET_ARCH_MIPS64
......
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