[ia32][x64] Reorganize macro-assembler functions and move to shared

Group all the SIMD (SSE/AVX) functions in macro-assembler-x64 together,
and move Ucomisd/Ucomiss to shared-macro-assembler.

Bug: v8:11589
Change-Id: Ia2246e816615aa8e143e94a1064838b2c314d8f0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3160698Reviewed-by: Adam Klein <adamk@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#76855}

src/codegen/ia32/macro-assembler-ia32.h

@@ -306,8 +306,6 @@ class V8_EXPORT_PRIVATE TurboAssembler
   AVX_OP(Pcmpeqb, pcmpeqb)
   AVX_OP(Pcmpeqw, pcmpeqw)
   AVX_OP(Pcmpeqd, pcmpeqd)
-  AVX_OP(Ucomisd, ucomisd)
-  AVX_OP(Ucomiss, ucomiss)
   AVX_OP_SSE4_1(Pcmpeqq, pcmpeqq)
 
 // Macro for instructions that have 2 operands for AVX version and 1 operand for

src/codegen/shared-ia32-x64/macro-assembler-shared-ia32-x64.h

@@ -327,6 +327,8 @@ class V8_EXPORT_PRIVATE SharedTurboAssembler : public TurboAssemblerBase {
   AVX_OP(Subps, subps)
   AVX_OP(Subsd, subsd)
   AVX_OP(Subss, subss)
+  AVX_OP(Ucomisd, ucomisd)
+  AVX_OP(Ucomiss, ucomiss)
   AVX_OP(Unpcklps, unpcklps)
   AVX_OP(Xorpd, xorpd)
   AVX_OP(Xorps, xorps)

src/codegen/x64/macro-assembler-x64.h

@@ -61,24 +61,6 @@ class V8_EXPORT_PRIVATE TurboAssembler
     : public SharedTurboAssemblerBase<TurboAssembler> {
  public:
   using SharedTurboAssemblerBase<TurboAssembler>::SharedTurboAssemblerBase;
-  AVX_OP(Ucomisd, ucomisd)
-  AVX_OP(Ucomiss, ucomiss)
-
-  // Define movq here instead of using AVX_OP. movq is defined using templates
-  // and there is a function template `void movq(P1)`, while technically
-  // impossible, will be selected when deducing the arguments for AvxHelper.
-  void Movq(XMMRegister dst, Register src);
-  void Movq(Register dst, XMMRegister src);
-  void Pextrq(Register dst, XMMRegister src, int8_t imm8);
-
-  void F64x2Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2,
-                 XMMRegister src3, XMMRegister tmp);
-  void F64x2Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2,
-                 XMMRegister src3, XMMRegister tmp);
-  void F32x4Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2,
-                 XMMRegister src3, XMMRegister tmp);
-  void F32x4Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2,
-                 XMMRegister src3, XMMRegister tmp);
 
   void PushReturnAddressFrom(Register src) { pushq(src); }
   void PopReturnAddressTo(Register dst) { popq(dst); }
@@ -137,6 +119,11 @@ class V8_EXPORT_PRIVATE TurboAssembler
                      Label* condition_met,
                      Label::Distance condition_met_distance = Label::kFar);
 
+  // Define movq here instead of using AVX_OP. movq is defined using templates
+  // and there is a function template `void movq(P1)`, while technically
+  // impossible, will be selected when deducing the arguments for AvxHelper.
+  void Movq(XMMRegister dst, Register src);
+  void Movq(Register dst, XMMRegister src);
   void Movdqa(XMMRegister dst, Operand src);
   void Movdqa(XMMRegister dst, XMMRegister src);
 
@@ -179,6 +166,28 @@ class V8_EXPORT_PRIVATE TurboAssembler
   void Cvtlsi2sd(XMMRegister dst, Register src);
   void Cvtlsi2sd(XMMRegister dst, Operand src);
 
+  void PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8);
+  void Pextrq(Register dst, XMMRegister src, int8_t imm8);
+
+  void PinsrdPreSse41(XMMRegister dst, Register src2, uint8_t imm8,
+                      uint32_t* load_pc_offset = nullptr);
+  void PinsrdPreSse41(XMMRegister dst, Operand src2, uint8_t imm8,
+                      uint32_t* load_pc_offset = nullptr);
+
+  void Pinsrq(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8,
+              uint32_t* load_pc_offset = nullptr);
+  void Pinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8,
+              uint32_t* load_pc_offset = nullptr);
+
+  void F64x2Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2,
+                 XMMRegister src3, XMMRegister tmp);
+  void F64x2Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2,
+                 XMMRegister src3, XMMRegister tmp);
+  void F32x4Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2,
+                 XMMRegister src3, XMMRegister tmp);
+  void F32x4Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2,
+                 XMMRegister src3, XMMRegister tmp);
+
   void Lzcntq(Register dst, Register src);
   void Lzcntq(Register dst, Operand src);
   void Lzcntl(Register dst, Register src);
@@ -412,18 +421,6 @@ class V8_EXPORT_PRIVATE TurboAssembler
   void Trap();
   void DebugBreak();
 
-  // Non-SSE2 instructions.
-  void PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8);
-
-  void PinsrdPreSse41(XMMRegister dst, Register src2, uint8_t imm8,
-                      uint32_t* load_pc_offset = nullptr);
-  void PinsrdPreSse41(XMMRegister dst, Operand src2, uint8_t imm8,
-                      uint32_t* load_pc_offset = nullptr);
-  void Pinsrq(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8,
-              uint32_t* load_pc_offset = nullptr);
-  void Pinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8,
-              uint32_t* load_pc_offset = nullptr);
-
   void CompareRoot(Register with, RootIndex index);
   void CompareRoot(Operand with, RootIndex index);
 

src/wasm/baseline/x64/liftoff-assembler-x64.h

@@ -2183,7 +2183,7 @@ void LiftoffAssembler::emit_i64_set_cond(LiftoffCondition liftoff_cond,
 }
 
 namespace liftoff {
-template <void (TurboAssembler::*cmp_op)(DoubleRegister, DoubleRegister)>
+template <void (SharedTurboAssembler::*cmp_op)(DoubleRegister, DoubleRegister)>
 void EmitFloatSetCond(LiftoffAssembler* assm, Condition cond, Register dst,
                       DoubleRegister lhs, DoubleRegister rhs) {
   Label cont;