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Commit 2b39e305 authored by Milad Fa's avatar Milad Fa Committed by Commit Bot
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PPC: [wasm-simd] Load specific amount of data for LoadTransform 

In this CL we fix the emitted code for Load Splat and Load Extend.
Load Splat loads a byte, half word, word or double word based
on the specific opcode.

Load Extend always loads a double word and then unpacks it
accordingly.

Change-Id: Ic1619c81a58f4997d69612f08edb6975d17e8bb3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2568132Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71543}
parent a90fdd2c
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Showing with 79 additions and 47 deletions
src/codegen/ppc/assembler-ppc.cc
View file @ 2b39e305
......@@ -1801,6 +1801,30 @@ void Assembler::lxvd(const Simd128Register rt, const MemOperand& src) {
TX);
}
void Assembler::lxsdx(const Simd128Register rt, const MemOperand& src) {
int TX = 1;
emit(LXSDX | rt.code() * B21 | src.ra().code() * B16 | src.rb().code() * B11 |
TX);
}
void Assembler::lxsibzx(const Simd128Register rt, const MemOperand& src) {
int TX = 1;
emit(LXSIBZX | rt.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | TX);
}
void Assembler::lxsihzx(const Simd128Register rt, const MemOperand& src) {
int TX = 1;
emit(LXSIHZX | rt.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | TX);
}
void Assembler::lxsiwzx(const Simd128Register rt, const MemOperand& src) {
int TX = 1;
emit(LXSIWZX | rt.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | TX);
}
void Assembler::stxvd(const Simd128Register rt, const MemOperand& dst) {
int SX = 1;
emit(STXVD | rt.code() * B21 | dst.ra().code() * B16 | dst.rb().code() * B11 |
......
src/codegen/ppc/assembler-ppc.h
View file @ 2b39e305
......@@ -1022,6 +1022,10 @@ class Assembler : public AssemblerBase {
void mtvsrd(const Simd128Register rt, const Register ra);
void mtvsrdd(const Simd128Register rt, const Register ra, const Register rb);
void lxvd(const Simd128Register rt, const MemOperand& src);
void lxsdx(const Simd128Register rt, const MemOperand& src);
void lxsibzx(const Simd128Register rt, const MemOperand& src);
void lxsihzx(const Simd128Register rt, const MemOperand& src);
void lxsiwzx(const Simd128Register rt, const MemOperand& src);
void stxvd(const Simd128Register rt, const MemOperand& src);
void xxspltib(const Simd128Register rt, const Operand& imm);
......
src/codegen/ppc/constants-ppc.h
View file @ 2b39e305
......@@ -1972,36 +1972,40 @@ using Instr = uint32_t;
PPC_VA_OPCODE_A_FORM_LIST(V) \
PPC_VA_OPCODE_UNUSED_LIST(V)
#define PPC_XX1_OPCODE_LIST(V) \
/* Load VSR Scalar Doubleword Indexed */ \
V(lxsdx, LXSDX, 0x7C000498) \
/* Load VSX Scalar as Integer Word Algebraic Indexed */ \
V(lxsiwax, LXSIWAX, 0x7C000098) \
/* Load VSX Scalar as Integer Word and Zero Indexed */ \
V(lxsiwzx, LXSIWZX, 0x7C000018) \
/* Load VSX Scalar Single-Precision Indexed */ \
V(lxsspx, LXSSPX, 0x7C000418) \
/* Load VSR Vector Doubleword*2 Indexed */ \
V(lxvd, LXVD, 0x7C000698) \
/* Load VSR Vector Doubleword & Splat Indexed */ \
V(lxvdsx, LXVDSX, 0x7C000298) \
/* Load VSR Vector Word*4 Indexed */ \
V(lxvw, LXVW, 0x7C000618) \
/* Move From VSR Doubleword */ \
V(mfvsrd, MFVSRD, 0x7C000066) \
/* Move From VSR Word and Zero */ \
V(mfvsrwz, MFVSRWZ, 0x7C0000E6) \
/* Store VSR Scalar Doubleword Indexed */ \
V(stxsdx, STXSDX, 0x7C000598) \
/* Store VSX Scalar as Integer Word Indexed */ \
V(stxsiwx, STXSIWX, 0x7C000118) \
/* Store VSR Scalar Word Indexed */ \
V(stxsspx, STXSSPX, 0x7C000518) \
/* Store VSR Vector Doubleword*2 Indexed */ \
V(stxvd, STXVD, 0x7C000798) \
/* Store VSR Vector Word*4 Indexed */ \
V(stxvw, STXVW, 0x7C000718) \
/* Vector Splat Immediate Byte */ \
#define PPC_XX1_OPCODE_LIST(V) \
/* Load VSR Scalar Doubleword Indexed */ \
V(lxsdx, LXSDX, 0x7C000498) \
/* Load VSX Scalar as Integer Word Algebraic Indexed */ \
V(lxsiwax, LXSIWAX, 0x7C000098) \
/* Load VSX Scalar as Integer Byte & Zero Indexed */ \
V(lxsibzx, LXSIBZX, 0x7C00061A) \
/* Load VSX Scalar as Integer Halfword & Zero Indexed */ \
V(lxsihzx, LXSIHZX, 0x7C00065A) \
/* Load VSX Scalar as Integer Word and Zero Indexed */ \
V(lxsiwzx, LXSIWZX, 0x7C000018) \
/* Load VSX Scalar Single-Precision Indexed */ \
V(lxsspx, LXSSPX, 0x7C000418) \
/* Load VSR Vector Doubleword*2 Indexed */ \
V(lxvd, LXVD, 0x7C000698) \
/* Load VSR Vector Doubleword & Splat Indexed */ \
V(lxvdsx, LXVDSX, 0x7C000298) \
/* Load VSR Vector Word*4 Indexed */ \
V(lxvw, LXVW, 0x7C000618) \
/* Move From VSR Doubleword */ \
V(mfvsrd, MFVSRD, 0x7C000066) \
/* Move From VSR Word and Zero */ \
V(mfvsrwz, MFVSRWZ, 0x7C0000E6) \
/* Store VSR Scalar Doubleword Indexed */ \
V(stxsdx, STXSDX, 0x7C000598) \
/* Store VSX Scalar as Integer Word Indexed */ \
V(stxsiwx, STXSIWX, 0x7C000118) \
/* Store VSR Scalar Word Indexed */ \
V(stxsspx, STXSSPX, 0x7C000518) \
/* Store VSR Vector Doubleword*2 Indexed */ \
V(stxvd, STXVD, 0x7C000798) \
/* Store VSR Vector Word*4 Indexed */ \
V(stxvw, STXVW, 0x7C000718) \
/* Vector Splat Immediate Byte */ \
V(xxspltib, XXSPLTIB, 0xF00002D1)
#define PPC_B_OPCODE_LIST(V) \
......
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ 2b39e305
......@@ -3476,45 +3476,45 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vsel(dst, src0, src1, kScratchDoubleReg);
break;
}
#define ASSEMBLE_LOAD_TRANSFORM(scratch) \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode); \
DCHECK_EQ(mode, kMode_MRR); \
__ lxvd(scratch, operand);
#define ASSEMBLE_LOAD_TRANSFORM(scratch, load_instr) \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode); \
DCHECK_EQ(mode, kMode_MRR); \
__ load_instr(scratch, operand);
case kPPC_S128Load8Splat: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsibzx)
__ vspltb(dst, kScratchDoubleReg, Operand(7));
break;
}
case kPPC_S128Load16Splat: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsihzx)
__ vsplth(dst, kScratchDoubleReg, Operand(3));
break;
}
case kPPC_S128Load32Splat: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsiwzx)
__ vspltw(dst, kScratchDoubleReg, Operand(1));
break;
}
case kPPC_S128Load64Splat: {
constexpr int lane_width_in_bytes = 8;
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(dst)
ASSEMBLE_LOAD_TRANSFORM(dst, lxsdx)
__ vinsertd(dst, dst, Operand(1 * lane_width_in_bytes));
break;
}
case kPPC_S128Load8x8S: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vupkhsb(dst, kScratchDoubleReg);
break;
}
case kPPC_S128Load8x8U: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vupkhsb(dst, kScratchDoubleReg);
// Zero extend.
__ li(ip, Operand(0xFF));
......@@ -3525,13 +3525,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kPPC_S128Load16x4S: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vupkhsh(dst, kScratchDoubleReg);
break;
}
case kPPC_S128Load16x4U: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vupkhsh(dst, kScratchDoubleReg);
// Zero extend.
__ mov(ip, Operand(0xFFFF));
......@@ -3543,14 +3543,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kPPC_S128Load32x2S: {
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vupkhsw(dst, kScratchDoubleReg);
break;
}
case kPPC_S128Load32x2U: {
constexpr int lane_width_in_bytes = 8;
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vupkhsw(dst, kScratchDoubleReg);
// Zero extend.
__ mov(ip, Operand(0xFFFFFFFF));
......@@ -3563,7 +3563,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kPPC_S128Load32Zero: {
constexpr int lane_width_in_bytes = 4;
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsiwzx)
__ vxor(dst, dst, dst);
__ vinsertw(dst, kScratchDoubleReg, Operand(3 * lane_width_in_bytes));
break;
......@@ -3571,7 +3571,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kPPC_S128Load64Zero: {
constexpr int lane_width_in_bytes = 8;
Simd128Register dst = i.OutputSimd128Register();
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg, lxsdx)
__ vxor(dst, dst, dst);
__ vinsertd(dst, kScratchDoubleReg, Operand(1 * lane_width_in_bytes));
break;
......
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