S390: Fix CEBR sim to treat operands as floats

Fix bug in simulator which incorrectly interpreted the operands
for CEBR (Float32 compare) as 64-bit doubles.  Add missing
disassembler case for CEBR as well.

R=jyan@ca.ibm.com,michael_dawson@ca.ibm.com,mbrandy@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1844473002

Cr-Commit-Position: refs/heads/master@{#35106}

src/s390/disasm-s390.cc

@@ -961,6 +961,9 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
     case CDBR:
       Format(instr, "cdbr\t'f5,'f6");
       break;
+    case CEBR:
+      Format(instr, "cebr\t'f5,'f6");
+      break;
     case SQDBR:
       Format(instr, "sqdbr\t'f5,'f6");
       break;

src/s390/simulator-s390.cc

@@ -3406,10 +3406,10 @@ bool Simulator::DecodeFourByteFloatingPoint(Instruction* instr) {
           SetS390ConditionCode<double>(r1_val, r2_val);
         }
       } else if (op == CEBR) {
-        if (isNaN(r1_val) || isNaN(r2_val)) {
+        if (isNaN(fr1_val) || isNaN(fr2_val)) {
           condition_reg_ = CC_OF;
         } else {
-          SetS390ConditionCode<float>(r1_val, r2_val);
+          SetS390ConditionCode<float>(fr1_val, fr2_val);
         }
       } else if (op == CDGBR) {
         int64_t r2_val = get_register(r2);