ARM: Change signature for vmov.32 function in the assembler

The assembler has 8 different vmov variants. The one for vmov.32 and for moving
an immediate into a double reg only differs in the type of the second
paremeter: vmov.32 takes an int, the other takes a double.

The situation is dangerous because C++ will happily implicitly convert between
int and double.

This patch changes the signature of the vmov.32 assembler function so that it
cannot be confused with the other vmovs.

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12255031
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13668 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

src/arm/assembler-arm.cc

@@ -2121,9 +2121,9 @@ void Assembler::vmov(const DwVfpRegister dst,
         // directly to the D register using vmov.32.
         // Note: This may be slower, so we only do this when we have to.
         mov(ip, Operand(lo));
-        vmov(dst, 0, ip, cond);
+        vmov(dst, VmovIndexLo, ip, cond);
         mov(ip, Operand(hi));
-        vmov(dst, 1, ip, cond);
+        vmov(dst, VmovIndexHi, ip, cond);
       }
     } else {
       // Move the low and high parts of the double to a D register in one
@@ -2167,7 +2167,7 @@ void Assembler::vmov(const DwVfpRegister dst,
 
 
 void Assembler::vmov(const DwVfpRegister dst,
-                     int index,
+                     const VmovIndex index,
                      const Register src,
                      const Condition cond) {
   // Dd[index] = Rt
@@ -2175,11 +2175,11 @@ void Assembler::vmov(const DwVfpRegister dst,
   // cond(31-28) | 1110(27-24) | 0(23) | opc1=0index(22-21) | 0(20) |
   // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0)
   ASSERT(CpuFeatures::IsEnabled(VFP2));
-  ASSERT(index == 0 || index == 1);
+  ASSERT(index.index == 0 || index.index == 1);
   int vd, d;
   dst.split_code(&vd, &d);
-  emit(cond | 0xE*B24 | index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 | d*B7 |
-       B4);
+  emit(cond | 0xE*B24 | index.index*B21 | vd*B16 | src.code()*B12 | 0xB*B8 |
+       d*B7 | B4);
 }
 
 

src/arm/assembler-arm.h

@@ -637,7 +637,11 @@ extern const Instr kCmpCmnFlip;
 extern const Instr kAddSubFlip;
 extern const Instr kAndBicFlip;
 
-
+struct VmovIndex {
+  unsigned char index;
+};
+const VmovIndex VmovIndexLo = { 0 };
+const VmovIndex VmovIndexHi = { 1 };
 
 class Assembler : public AssemblerBase {
  public:
@@ -1071,7 +1075,7 @@ class Assembler : public AssemblerBase {
             const DwVfpRegister src,
             const Condition cond = al);
   void vmov(const DwVfpRegister dst,
-            int index,
+            const VmovIndex index,
             const Register src,
             const Condition cond = al);
   void vmov(const DwVfpRegister dst,

test/cctest/test-assembler-arm.cc

@@ -1106,8 +1106,8 @@ TEST(13) {
     __ vmov(d21, 16.0);
     __ mov(r1, Operand(372106121));
     __ mov(r2, Operand(1079146608));
-    __ vmov(d22, 0, r1);
-    __ vmov(d22, 1, r2);
+    __ vmov(d22, VmovIndexLo, r1);
+    __ vmov(d22, VmovIndexHi, r2);
     __ add(r4, r0, Operand(OFFSET_OF(T, i)));
     __ vstm(ia_w, r4, d20, d22);
 

test/cctest/test-disasm-arm.cc

@@ -492,9 +492,9 @@ TEST(Vfp) {
     COMPARE(vmov(d2, -13.0),
             "eeba2b0a       vmov.f64 d2, #-13");
 
-    COMPARE(vmov(d0, 0, r0),
+    COMPARE(vmov(d0, VmovIndexLo, r0),
             "ee000b10       vmov.32 d0[0], r0");
-    COMPARE(vmov(d0, 1, r0),
+    COMPARE(vmov(d0, VmovIndexHi, r0),
             "ee200b10       vmov.32 d0[1], r0");
 
     COMPARE(vldr(s0, r0, 0),
@@ -619,9 +619,9 @@ TEST(Vfp) {
       COMPARE(vmov(d30, 16.0),
               "eef3eb00       vmov.f64 d30, #16");
 
-      COMPARE(vmov(d31, 0, r7),
+      COMPARE(vmov(d31, VmovIndexLo, r7),
               "ee0f7b90       vmov.32 d31[0], r7");
-      COMPARE(vmov(d31, 1, r7),
+      COMPARE(vmov(d31, VmovIndexHi, r7),
               "ee2f7b90       vmov.32 d31[1], r7");
 
       COMPARE(vldr(d25, r0, 0),