Commit 1fc5f92a authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

S390 [liftoff]: Implement simd i32 convert low to fp

Change-Id: I6c24b0930d489a9af7e877e783663f2493168604
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3417920Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78793}
parent c1e5f3f1
...@@ -5537,6 +5537,18 @@ void TurboAssembler::I16x8BitMask(Register dst, Simd128Register src, ...@@ -5537,6 +5537,18 @@ void TurboAssembler::I16x8BitMask(Register dst, Simd128Register src,
vlgv(dst, scratch2, MemOperand(r0, 7), Condition(0)); vlgv(dst, scratch2, MemOperand(r0, 7), Condition(0));
} }
void TurboAssembler::F64x2ConvertLowI32x4S(Simd128Register dst,
Simd128Register src) {
vupl(dst, src, Condition(0), Condition(0), Condition(2));
vcdg(dst, dst, Condition(4), Condition(0), Condition(3));
}
void TurboAssembler::F64x2ConvertLowI32x4U(Simd128Register dst,
Simd128Register src) {
vupll(dst, src, Condition(0), Condition(0), Condition(2));
vcdlg(dst, dst, Condition(4), Condition(0), Condition(3));
}
void TurboAssembler::I8x16BitMask(Register dst, Simd128Register src, void TurboAssembler::I8x16BitMask(Register dst, Simd128Register src,
Register scratch1, Register scratch2, Register scratch1, Register scratch2,
Simd128Register scratch3) { Simd128Register scratch3) {
......
...@@ -1114,29 +1114,31 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ...@@ -1114,29 +1114,31 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void I8x16BitMask(Register dst, Simd128Register src, Register scratch1, void I8x16BitMask(Register dst, Simd128Register src, Register scratch1,
Register scratch2, Simd128Register scratch3); Register scratch2, Simd128Register scratch3);
#define SIMD_UNOP_LIST(V) \ #define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \ V(F64x2Abs) \
V(F64x2Neg) \ V(F64x2Neg) \
V(F64x2Sqrt) \ V(F64x2Sqrt) \
V(F64x2Ceil) \ V(F64x2Ceil) \
V(F64x2Floor) \ V(F64x2Floor) \
V(F64x2Trunc) \ V(F64x2Trunc) \
V(F64x2NearestInt) \ V(F64x2NearestInt) \
V(F32x4Abs) \ V(F64x2ConvertLowI32x4S) \
V(F32x4Neg) \ V(F64x2ConvertLowI32x4U) \
V(F32x4Sqrt) \ V(F32x4Abs) \
V(F32x4Ceil) \ V(F32x4Neg) \
V(F32x4Floor) \ V(F32x4Sqrt) \
V(F32x4Trunc) \ V(F32x4Ceil) \
V(F32x4NearestInt) \ V(F32x4Floor) \
V(I64x2Abs) \ V(F32x4Trunc) \
V(I32x4Abs) \ V(F32x4NearestInt) \
V(I16x8Abs) \ V(I64x2Abs) \
V(I8x16Abs) \ V(I32x4Abs) \
V(I64x2Neg) \ V(I16x8Abs) \
V(I32x4Neg) \ V(I8x16Abs) \
V(I16x8Neg) \ V(I64x2Neg) \
V(I8x16Neg) \ V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg) \
V(S128Not) V(S128Not)
#define PROTOTYPE_SIMD_UNOP(name) \ #define PROTOTYPE_SIMD_UNOP(name) \
......
...@@ -3257,17 +3257,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3257,17 +3257,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kS390_F64x2ConvertLowI32x4S: { case kS390_F64x2ConvertLowI32x4S: {
__ vupl(kScratchDoubleReg, i.InputSimd128Register(0), Condition(0), __ F64x2ConvertLowI32x4S(i.OutputSimd128Register(),
Condition(0), Condition(2)); i.InputSimd128Register(0));
__ vcdg(i.OutputSimd128Register(), kScratchDoubleReg, Condition(4),
Condition(0), Condition(3));
break; break;
} }
case kS390_F64x2ConvertLowI32x4U: { case kS390_F64x2ConvertLowI32x4U: {
__ vupll(kScratchDoubleReg, i.InputSimd128Register(0), Condition(0), __ F64x2ConvertLowI32x4U(i.OutputSimd128Register(),
Condition(0), Condition(2)); i.InputSimd128Register(0));
__ vcdlg(i.OutputSimd128Register(), kScratchDoubleReg, Condition(4),
Condition(0), Condition(3));
break; break;
} }
case kS390_F64x2PromoteLowF32x4: { case kS390_F64x2PromoteLowF32x4: {
......
...@@ -2515,12 +2515,12 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst, ...@@ -2515,12 +2515,12 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_s(LiftoffRegister dst, void LiftoffAssembler::emit_f64x2_convert_low_i32x4_s(LiftoffRegister dst,
LiftoffRegister src) { LiftoffRegister src) {
bailout(kSimd, "f64x2.convert_low_i32x4_s"); F64x2ConvertLowI32x4S(dst.fp(), src.fp());
} }
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_u(LiftoffRegister dst, void LiftoffAssembler::emit_f64x2_convert_low_i32x4_u(LiftoffRegister dst,
LiftoffRegister src) { LiftoffRegister src) {
bailout(kSimd, "f64x2.convert_low_i32x4_u"); F64x2ConvertLowI32x4U(dst.fp(), src.fp());
} }
void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst, void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
......
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