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Commit 1fa2d2f3 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [simd]: cleanup the instruction selector 

This CL includes the following changes:
- Avoid using `UniqueRegister` as much as possible
- Try to group opcodes under Binary or Unary when possible

Separate selectors are added to use `UniqueRegister` when necessary
mainly when `Temp` registers are used. This is to make sure temp, dst
and src registers are allocated differently and cannot be overwritten
during codegen.

Some codegen ops had to also be modified to avoid using `Temp`
registers.

Change-Id: I4d5bdec58cb4874e7c3d344091cde8c8a9a4d01b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3024149Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75723}
parent dc318df3
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Showing with 170 additions and 214 deletions
src/compiler/backend/s390/code-generator-s390.cc
View file @ 1fa2d2f3
...@@ -2224,14 +2224,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2224,14 +2224,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_LoadReverseSimd128: { case kS390_LoadReverseSimd128: {
AddressingMode mode = kMode_None; AddressingMode mode = kMode_None;
MemOperand operand = i.MemoryOperand(&mode); MemOperand operand = i.MemoryOperand(&mode);
Simd128Register dst = i.OutputSimd128Register();
if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2) && if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2) &&
is_uint12(operand.offset())) { is_uint12(operand.offset())) {
__ vlbr(i.OutputSimd128Register(), operand, Condition(4)); __ vlbr(dst, operand, Condition(4));
} else { } else {
__ lrvg(r0, operand); __ lrvg(r0, operand);
__ lrvg(r1, MemOperand(operand.rx(), operand.rb(), __ lrvg(r1, MemOperand(operand.rx(), operand.rb(),
operand.offset() + kSystemPointerSize)); operand.offset() + kSystemPointerSize));
__ vlvgp(i.OutputSimd128Register(), r1, r0); __ vlvgp(dst, r1, r0);
} }
break; break;
} }
...@@ -2587,8 +2588,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2587,8 +2588,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (src != dst) { if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0)); __ vlr(dst, src, Condition(0), Condition(0), Condition(0));
} }
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2), __ vlvg(dst, i.InputRegister(2), MemOperand(r0, 1 - i.InputInt8(1)),
MemOperand(r0, 1 - i.InputInt8(1)), Condition(3)); Condition(3));
break; break;
} }
case kS390_I32x4ReplaceLane: { case kS390_I32x4ReplaceLane: {
...@@ -2597,8 +2598,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2597,8 +2598,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (src != dst) { if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0)); __ vlr(dst, src, Condition(0), Condition(0), Condition(0));
} }
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2), __ vlvg(dst, i.InputRegister(2), MemOperand(r0, 3 - i.InputInt8(1)),
MemOperand(r0, 3 - i.InputInt8(1)), Condition(2)); Condition(2));
break; break;
} }
case kS390_I16x8ReplaceLane: { case kS390_I16x8ReplaceLane: {
...@@ -2607,8 +2608,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2607,8 +2608,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (src != dst) { if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0)); __ vlr(dst, src, Condition(0), Condition(0), Condition(0));
} }
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2), __ vlvg(dst, i.InputRegister(2), MemOperand(r0, 7 - i.InputInt8(1)),
MemOperand(r0, 7 - i.InputInt8(1)), Condition(1)); Condition(1));
break; break;
} }
case kS390_I8x16ReplaceLane: { case kS390_I8x16ReplaceLane: {
...@@ -2617,8 +2618,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2617,8 +2618,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (src != dst) { if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0)); __ vlr(dst, src, Condition(0), Condition(0), Condition(0));
} }
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2), __ vlvg(dst, i.InputRegister(2), MemOperand(r0, 15 - i.InputInt8(1)),
MemOperand(r0, 15 - i.InputInt8(1)), Condition(0)); Condition(0));
break; break;
} }
// vector binops // vector binops
...@@ -3195,14 +3196,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3195,14 +3196,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kS390_F32x4RecipSqrtApprox: { case kS390_F32x4RecipSqrtApprox: {
DoubleRegister tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); Simd128Register dst = i.OutputSimd128Register();
__ vfsq(tempFPReg1, i.InputSimd128Register(0), Condition(0), Condition(0), __ vfsq(dst, i.InputSimd128Register(0), Condition(0), Condition(0),
Condition(2)); Condition(2));
__ mov(kScratchReg, Operand(1)); __ mov(kScratchReg, Operand(1));
__ ConvertIntToFloat(kScratchDoubleReg, kScratchReg); __ ConvertIntToFloat(kScratchDoubleReg, kScratchReg);
__ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(2)); __ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(2));
__ vfd(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1, __ vfd(dst, kScratchDoubleReg, dst, Condition(0), Condition(0),
Condition(0), Condition(0), Condition(2)); Condition(2));
break; break;
} }
case kS390_F32x4Sqrt: { case kS390_F32x4Sqrt: {
...@@ -3240,18 +3241,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3240,18 +3241,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_V128AnyTrue: { case kS390_V128AnyTrue: {
Simd128Register src = i.InputSimd128Register(0); Simd128Register src = i.InputSimd128Register(0);
Register dst = i.OutputRegister(); Register dst = i.OutputRegister();
Register temp = i.TempRegister(0);
__ mov(dst, Operand(1)); __ mov(dst, Operand(1));
__ xgr(temp, temp); __ xgr(kScratchReg, kScratchReg);
__ vtm(src, src, Condition(0), Condition(0), Condition(0)); __ vtm(src, src, Condition(0), Condition(0), Condition(0));
__ locgr(Condition(8), dst, temp); __ locgr(Condition(8), dst, kScratchReg);
break; break;
} }
#define SIMD_ALL_TRUE(mode) \ #define SIMD_ALL_TRUE(mode) \
Simd128Register src = i.InputSimd128Register(0); \ Simd128Register src = i.InputSimd128Register(0); \
Register dst = i.OutputRegister(); \ Register dst = i.OutputRegister(); \
Register temp = i.TempRegister(0); \ __ mov(kScratchReg, Operand(1)); \
__ mov(temp, Operand(1)); \
__ xgr(dst, dst); \ __ xgr(dst, dst); \
__ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, Condition(0), \ __ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, Condition(0), \
Condition(0), Condition(2)); \ Condition(0), Condition(2)); \
...@@ -3259,7 +3258,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3259,7 +3258,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(mode)); \ Condition(mode)); \
__ vtm(kScratchDoubleReg, kScratchDoubleReg, Condition(0), Condition(0), \ __ vtm(kScratchDoubleReg, kScratchDoubleReg, Condition(0), Condition(0), \
Condition(0)); \ Condition(0)); \
__ locgr(Condition(8), dst, temp); __ locgr(Condition(8), dst, kScratchReg);
case kS390_I64x2AllTrue: { case kS390_I64x2AllTrue: {
SIMD_ALL_TRUE(3) SIMD_ALL_TRUE(3)
break; break;
...@@ -3344,7 +3343,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3344,7 +3343,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_I32x4SConvertF32x4: { case kS390_I32x4SConvertF32x4: {
Simd128Register src = i.InputSimd128Register(0); Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); Simd128Register tempFPReg1 = i.ToDoubleRegister(instr->TempAt(0));
// NaN to 0 // NaN to 0
__ vlr(kScratchDoubleReg, src, Condition(0), Condition(0), Condition(0)); __ vlr(kScratchDoubleReg, src, Condition(0), Condition(0), Condition(0));
__ vfce(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, __ vfce(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
...@@ -3362,7 +3361,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3362,7 +3361,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_I32x4UConvertF32x4: { case kS390_I32x4UConvertF32x4: {
Simd128Register src = i.InputSimd128Register(0); Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); Simd128Register tempFPReg1 = i.ToDoubleRegister(instr->TempAt(0));
// NaN to 0, negative to 0 // NaN to 0, negative to 0
__ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, __ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
Condition(0), Condition(0), Condition(0)); Condition(0), Condition(0), Condition(0));
...@@ -3576,8 +3575,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3576,8 +3575,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
uint64_t high = make_uint64(i.InputUint32(5), i.InputUint32(4)); uint64_t high = make_uint64(i.InputUint32(5), i.InputUint32(4));
__ mov(r0, Operand(low)); __ mov(r0, Operand(low));
__ mov(ip, Operand(high)); __ mov(ip, Operand(high));
__ vlvgp(dst, ip, r0); __ vlvgp(kScratchDoubleReg, ip, r0);
__ vperm(dst, src0, src1, dst, Condition(0), Condition(0)); __ vperm(dst, src0, src1, kScratchDoubleReg, Condition(0), Condition(0));
break; break;
} }
case kS390_I8x16Swizzle: { case kS390_I8x16Swizzle: {
...@@ -3720,14 +3719,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3720,14 +3719,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(0), Condition(0), Condition(2)); Condition(0), Condition(0), Condition(2));
break; break;
} }
#define EXT_MUL(mul_even, mul_odd, merge, mode) \ #define EXT_MUL(mul_even, mul_odd, merge, mode) \
Simd128Register dst = i.OutputSimd128Register(), \ Simd128Register dst = i.OutputSimd128Register(), \
src0 = i.InputSimd128Register(0), \ src0 = i.InputSimd128Register(0), \
src1 = i.InputSimd128Register(1); \ src1 = i.InputSimd128Register(1); \
__ mul_even(dst, src0, src1, Condition(0), Condition(0), Condition(mode)); \ __ mul_even(kScratchDoubleReg, src0, src1, Condition(0), Condition(0), \
__ mul_odd(kScratchDoubleReg, src0, src1, Condition(0), Condition(0), \ Condition(mode)); \
Condition(mode)); \ __ mul_odd(dst, src0, src1, Condition(0), Condition(0), Condition(mode)); \
__ merge(dst, dst, kScratchDoubleReg, Condition(0), Condition(0), \ __ merge(dst, kScratchDoubleReg, dst, Condition(0), Condition(0), \
Condition(mode + 1)); Condition(mode + 1));
case kS390_I64x2ExtMulLowI32x4S: { case kS390_I64x2ExtMulLowI32x4S: {
EXT_MUL(vme, vmo, vmrl, 2) EXT_MUL(vme, vmo, vmrl, 2)
...@@ -3783,12 +3782,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3783,12 +3782,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Simd128Register src = i.InputSimd128Register(0); \ Simd128Register src = i.InputSimd128Register(0); \
Simd128Register dst = i.OutputSimd128Register(); \ Simd128Register dst = i.OutputSimd128Register(); \
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); \ Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); \
__ vrepi(kScratchDoubleReg, Operand(1), Condition(lane_size)); \ __ vrepi(tempFPReg1, Operand(1), Condition(lane_size)); \
__ mul_even(tempFPReg1, src, kScratchDoubleReg, Condition(0), Condition(0), \ __ mul_even(kScratchDoubleReg, src, tempFPReg1, Condition(0), Condition(0), \
Condition(lane_size)); \ Condition(lane_size)); \
__ mul_odd(kScratchDoubleReg, src, kScratchDoubleReg, Condition(0), \ __ mul_odd(tempFPReg1, src, tempFPReg1, Condition(0), Condition(0), \
Condition(0), Condition(lane_size)); \ Condition(lane_size)); \
__ va(dst, tempFPReg1, kScratchDoubleReg, Condition(0), Condition(0), \ __ va(dst, kScratchDoubleReg, tempFPReg1, Condition(0), Condition(0), \
Condition(lane_size + 1)); Condition(lane_size + 1));
case kS390_I32x4ExtAddPairwiseI16x8S: { case kS390_I32x4ExtAddPairwiseI16x8S: {
EXT_ADD_PAIRWISE(1, vme, vmo) EXT_ADD_PAIRWISE(1, vme, vmo)
...@@ -3801,7 +3800,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3801,7 +3800,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(0), Condition(0), Condition(3)); Condition(0), Condition(0), Condition(3));
__ vsum(dst, src0, kScratchDoubleReg, Condition(0), Condition(0), __ vsum(dst, src0, kScratchDoubleReg, Condition(0), Condition(0),
Condition(1)); Condition(1));
break; break;
} }
case kS390_I16x8ExtAddPairwiseI8x16S: { case kS390_I16x8ExtAddPairwiseI8x16S: {
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ 1fa2d2f3
...@@ -2422,6 +2422,8 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2422,6 +2422,8 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(F64x2Le) \ V(F64x2Le) \
V(F64x2Min) \ V(F64x2Min) \
V(F64x2Max) \ V(F64x2Max) \
V(F64x2Pmin) \
V(F64x2Pmax) \
V(F32x4Add) \ V(F32x4Add) \
V(F32x4Sub) \ V(F32x4Sub) \
V(F32x4Mul) \ V(F32x4Mul) \
...@@ -2432,6 +2434,8 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2432,6 +2434,8 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(F32x4Div) \ V(F32x4Div) \
V(F32x4Min) \ V(F32x4Min) \
V(F32x4Max) \ V(F32x4Max) \
V(F32x4Pmin) \
V(F32x4Pmax) \
V(I64x2Add) \ V(I64x2Add) \
V(I64x2Sub) \ V(I64x2Sub) \
V(I64x2Mul) \ V(I64x2Mul) \
...@@ -2440,10 +2444,12 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2440,10 +2444,12 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I64x2ExtMulHighI32x4S) \ V(I64x2ExtMulHighI32x4S) \
V(I64x2ExtMulLowI32x4U) \ V(I64x2ExtMulLowI32x4U) \
V(I64x2ExtMulHighI32x4U) \ V(I64x2ExtMulHighI32x4U) \
V(I16x8Q15MulRSatS) \
V(I64x2Ne) \ V(I64x2Ne) \
V(I64x2GtS) \ V(I64x2GtS) \
V(I64x2GeS) \ V(I64x2GeS) \
V(I64x2Shl) \
V(I64x2ShrS) \
V(I64x2ShrU) \
V(I32x4Add) \ V(I32x4Add) \
V(I32x4Sub) \ V(I32x4Sub) \
V(I32x4Mul) \ V(I32x4Mul) \
...@@ -2457,11 +2463,13 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2457,11 +2463,13 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I32x4GeS) \ V(I32x4GeS) \
V(I32x4GtU) \ V(I32x4GtU) \
V(I32x4GeU) \ V(I32x4GeU) \
V(I32x4DotI16x8S) \
V(I32x4ExtMulLowI16x8S) \ V(I32x4ExtMulLowI16x8S) \
V(I32x4ExtMulHighI16x8S) \ V(I32x4ExtMulHighI16x8S) \
V(I32x4ExtMulLowI16x8U) \ V(I32x4ExtMulLowI16x8U) \
V(I32x4ExtMulHighI16x8U) \ V(I32x4ExtMulHighI16x8U) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Add) \ V(I16x8Add) \
V(I16x8Sub) \ V(I16x8Sub) \
V(I16x8Mul) \ V(I16x8Mul) \
...@@ -2476,16 +2484,14 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2476,16 +2484,14 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I16x8GtU) \ V(I16x8GtU) \
V(I16x8GeU) \ V(I16x8GeU) \
V(I16x8SConvertI32x4) \ V(I16x8SConvertI32x4) \
V(I16x8UConvertI32x4) \
V(I16x8AddSatS) \
V(I16x8SubSatS) \
V(I16x8AddSatU) \
V(I16x8SubSatU) \
V(I16x8RoundingAverageU) \ V(I16x8RoundingAverageU) \
V(I16x8ExtMulLowI8x16S) \ V(I16x8ExtMulLowI8x16S) \
V(I16x8ExtMulHighI8x16S) \ V(I16x8ExtMulHighI8x16S) \
V(I16x8ExtMulLowI8x16U) \ V(I16x8ExtMulLowI8x16U) \
V(I16x8ExtMulHighI8x16U) \ V(I16x8ExtMulHighI8x16U) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Add) \ V(I8x16Add) \
V(I8x16Sub) \ V(I8x16Sub) \
V(I8x16MinS) \ V(I8x16MinS) \
...@@ -2499,102 +2505,100 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2499,102 +2505,100 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I8x16GtU) \ V(I8x16GtU) \
V(I8x16GeU) \ V(I8x16GeU) \
V(I8x16SConvertI16x8) \ V(I8x16SConvertI16x8) \
V(I8x16UConvertI16x8) \
V(I8x16AddSatS) \
V(I8x16SubSatS) \
V(I8x16AddSatU) \
V(I8x16SubSatU) \
V(I8x16RoundingAverageU) \ V(I8x16RoundingAverageU) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU) \
V(S128And) \ V(S128And) \
V(S128Or) \ V(S128Or) \
V(S128Xor) \ V(S128Xor) \
V(S128AndNot) V(S128AndNot)
#define SIMD_UNOP_LIST(V) \ #define SIMD_BINOP_UNIQUE_REGISTER_LIST(V) \
V(F64x2Abs) \ V(I32x4DotI16x8S) \
V(F64x2Neg) \ V(I16x8AddSatS) \
V(F64x2Sqrt) \ V(I16x8SubSatS) \
V(F64x2Ceil) \ V(I16x8AddSatU) \
V(F64x2Floor) \ V(I16x8SubSatU) \
V(F64x2Trunc) \ V(I16x8Q15MulRSatS) \
V(F64x2NearestInt) \ V(I16x8UConvertI32x4) \
V(F64x2ConvertLowI32x4S) \ V(I8x16AddSatS) \
V(F64x2ConvertLowI32x4U) \ V(I8x16SubSatS) \
V(F64x2PromoteLowF32x4) \ V(I8x16AddSatU) \
V(F32x4Abs) \ V(I8x16SubSatU) \
V(F32x4Neg) \ V(I8x16Swizzle) \
V(F32x4RecipApprox) \ V(I8x16UConvertI16x8)
V(F32x4RecipSqrtApprox) \
V(F32x4Sqrt) \ #define SIMD_UNOP_LIST(V) \
V(F32x4Ceil) \ V(F64x2Abs) \
V(F32x4Floor) \ V(F64x2Neg) \
V(F32x4Trunc) \ V(F64x2Sqrt) \
V(F32x4NearestInt) \ V(F64x2Ceil) \
V(F32x4DemoteF64x2Zero) \ V(F64x2Floor) \
V(I64x2Neg) \ V(F64x2Trunc) \
V(I64x2SConvertI32x4Low) \ V(F64x2NearestInt) \
V(I64x2SConvertI32x4High) \ V(F64x2ConvertLowI32x4S) \
V(I64x2UConvertI32x4Low) \ V(F64x2ConvertLowI32x4U) \
V(I64x2UConvertI32x4High) \ V(F64x2PromoteLowF32x4) \
V(I64x2Abs) \ V(F64x2Splat) \
V(I32x4Neg) \ V(F32x4Abs) \
V(I32x4Abs) \ V(F32x4Neg) \
V(I32x4SConvertI16x8Low) \ V(F32x4RecipApprox) \
V(I32x4SConvertI16x8High) \ V(F32x4RecipSqrtApprox) \
V(I32x4UConvertI16x8Low) \ V(F32x4Sqrt) \
V(I32x4UConvertI16x8High) \ V(F32x4Ceil) \
V(I32x4TruncSatF64x2SZero) \ V(F32x4Floor) \
V(I32x4TruncSatF64x2UZero) \ V(F32x4Trunc) \
V(I32x4ExtAddPairwiseI16x8S) \ V(F32x4NearestInt) \
V(I32x4ExtAddPairwiseI16x8U) \ V(F32x4DemoteF64x2Zero) \
V(I16x8Neg) \ V(F32x4SConvertI32x4) \
V(I16x8Abs) \ V(F32x4UConvertI32x4) \
V(I16x8SConvertI8x16Low) \ V(F32x4Splat) \
V(I16x8SConvertI8x16High) \ V(I64x2Neg) \
V(I16x8UConvertI8x16Low) \ V(I64x2SConvertI32x4Low) \
V(I16x8UConvertI8x16High) \ V(I64x2SConvertI32x4High) \
V(I16x8ExtAddPairwiseI8x16S) \ V(I64x2UConvertI32x4Low) \
V(I16x8ExtAddPairwiseI8x16U) \ V(I64x2UConvertI32x4High) \
V(I8x16Neg) \ V(I64x2Abs) \
V(I8x16Abs) \ V(I64x2BitMask) \
V(I8x16Popcnt) \ V(I64x2Splat) \
V(S128Not) V(I64x2AllTrue) \
V(I32x4Neg) \
#define SIMD_SHIFT_LIST(V) \ V(I32x4Abs) \
V(I64x2Shl) \ V(I32x4SConvertI16x8Low) \
V(I64x2ShrS) \ V(I32x4SConvertI16x8High) \
V(I64x2ShrU) \ V(I32x4UConvertI16x8Low) \
V(I32x4Shl) \ V(I32x4UConvertI16x8High) \
V(I32x4ShrS) \ V(I32x4TruncSatF64x2SZero) \
V(I32x4ShrU) \ V(I32x4TruncSatF64x2UZero) \
V(I16x8Shl) \ V(I32x4BitMask) \
V(I16x8ShrS) \ V(I32x4Splat) \
V(I16x8ShrU) \ V(I32x4AllTrue) \
V(I8x16Shl) \ V(I16x8Neg) \
V(I8x16ShrS) \ V(I16x8Abs) \
V(I8x16ShrU) V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \
#define SIMD_BOOL_LIST(V) \ V(I16x8UConvertI8x16Low) \
V(V128AnyTrue) \ V(I16x8UConvertI8x16High) \
V(I64x2AllTrue) \ V(I16x8BitMask) \
V(I32x4AllTrue) \ V(I16x8Splat) \
V(I16x8AllTrue) \ V(I16x8AllTrue) \
V(I8x16AllTrue) V(I8x16Neg) \
V(I8x16Abs) \
#define SIMD_CONVERSION_LIST(V) \ V(I8x16Popcnt) \
V(I32x4SConvertF32x4) \ V(I8x16BitMask) \
V(I32x4UConvertF32x4) \ V(I8x16Splat) \
V(F32x4SConvertI32x4) \ V(I8x16AllTrue) \
V(F32x4UConvertI32x4) V(S128Not) \
V(V128AnyTrue)
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \ #define SIMD_UNOP_UNIQUE_REGISTER_LIST(V) \
S390OperandGenerator g(this); \ V(I32x4SConvertF32x4) \
Emit(kS390_##Type##Splat, g.DefineAsRegister(node), \ V(I32x4UConvertF32x4) \
g.UseRegister(node->InputAt(0))); \ V(I32x4ExtAddPairwiseI16x8S) \
} V(I32x4ExtAddPairwiseI16x8U) \
SIMD_TYPES(SIMD_VISIT_SPLAT) V(I16x8ExtAddPairwiseI8x16S) \
#undef SIMD_VISIT_SPLAT V(I16x8ExtAddPairwiseI8x16U)
#define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \ #define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \
void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \ void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
...@@ -2624,7 +2628,17 @@ SIMD_VISIT_EXTRACT_LANE(I8x16, S) ...@@ -2624,7 +2628,17 @@ SIMD_VISIT_EXTRACT_LANE(I8x16, S)
SIMD_TYPES(SIMD_VISIT_REPLACE_LANE) SIMD_TYPES(SIMD_VISIT_REPLACE_LANE)
#undef SIMD_VISIT_REPLACE_LANE #undef SIMD_VISIT_REPLACE_LANE
#define SIMD_VISIT_BINOP(Opcode) \ #define SIMD_VISIT_BINOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); \
}
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#undef SIMD_BINOP_LIST
#define SIMD_VISIT_BINOP_UNIQUE_REGISTER(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \ void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register(), \ InstructionOperand temps[] = {g.TempSimd128Register(), \
...@@ -2633,91 +2647,43 @@ SIMD_TYPES(SIMD_VISIT_REPLACE_LANE) ...@@ -2633,91 +2647,43 @@ SIMD_TYPES(SIMD_VISIT_REPLACE_LANE)
g.UseUniqueRegister(node->InputAt(0)), \ g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); \ g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); \
} }
SIMD_BINOP_LIST(SIMD_VISIT_BINOP) SIMD_BINOP_UNIQUE_REGISTER_LIST(SIMD_VISIT_BINOP_UNIQUE_REGISTER)
#undef SIMD_VISIT_BINOP #undef SIMD_VISIT_BINOP_UNIQUE_REGISTER
#undef SIMD_BINOP_LIST #undef SIMD_BINOP_UNIQUE_REGISTER_LIST
#define SIMD_VISIT_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), arraysize(temps), temps); \
}
SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_UNOP
#undef SIMD_UNOP_LIST
#define SIMD_VISIT_SHIFT(Opcode) \ #define SIMD_VISIT_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \ void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \ Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), \ g.UseRegister(node->InputAt(0))); \
g.UseUniqueRegister(node->InputAt(1))); \
} }
SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT) SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_SHIFT #undef SIMD_VISIT_UNOP
#undef SIMD_SHIFT_LIST #undef SIMD_UNOP_LIST
#define SIMD_VISIT_BOOL(Opcode) \ #define SIMD_VISIT_UNOP_UNIQUE_REGISTER(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \ void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempRegister()}; \ InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \ Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps); \ g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps); \
} }
SIMD_BOOL_LIST(SIMD_VISIT_BOOL) SIMD_UNOP_UNIQUE_REGISTER_LIST(SIMD_VISIT_UNOP_UNIQUE_REGISTER)
#undef SIMD_VISIT_BOOL #undef SIMD_VISIT_UNOP_UNIQUE_REGISTER
#undef SIMD_BOOL_LIST #undef SIMD_UNOP_UNIQUE_REGISTER_LIST
#define SIMD_VISIT_CONVERSION(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), arraysize(temps), temps); \
}
SIMD_CONVERSION_LIST(SIMD_VISIT_CONVERSION)
#undef SIMD_VISIT_CONVERSION
#undef SIMD_CONVERSION_LIST
#define SIMD_VISIT_QFMOP(Opcode) \ #define SIMD_VISIT_QFMOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \ void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineSameAsFirst(node), \ Emit(kS390_##Opcode, g.DefineSameAsFirst(node), \
g.UseUniqueRegister(node->InputAt(0)), \ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
g.UseUniqueRegister(node->InputAt(1)), \ g.UseRegister(node->InputAt(2))); \
g.UseRegister(node->InputAt(2))); \
} }
SIMD_VISIT_QFMOP(F64x2Qfma) SIMD_VISIT_QFMOP(F64x2Qfma)
SIMD_VISIT_QFMOP(F64x2Qfms) SIMD_VISIT_QFMOP(F64x2Qfms)
SIMD_VISIT_QFMOP(F32x4Qfma) SIMD_VISIT_QFMOP(F32x4Qfma)
SIMD_VISIT_QFMOP(F32x4Qfms) SIMD_VISIT_QFMOP(F32x4Qfms)
#undef SIMD_VISIT_QFMOP #undef SIMD_VISIT_QFMOP
#define SIMD_VISIT_BITMASK(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0))); \
}
SIMD_VISIT_BITMASK(I8x16BitMask)
SIMD_VISIT_BITMASK(I16x8BitMask)
SIMD_VISIT_BITMASK(I32x4BitMask)
SIMD_VISIT_BITMASK(I64x2BitMask)
#undef SIMD_VISIT_BITMASK
#define SIMD_VISIT_PMIN_MAX(Type) \
void InstructionSelector::Visit##Type(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Type, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); \
}
SIMD_VISIT_PMIN_MAX(F64x2Pmin)
SIMD_VISIT_PMIN_MAX(F32x4Pmin)
SIMD_VISIT_PMIN_MAX(F64x2Pmax)
SIMD_VISIT_PMIN_MAX(F32x4Pmax)
#undef SIMD_VISIT_PMIN_MAX
#undef SIMD_TYPES #undef SIMD_TYPES
#if V8_ENABLE_WEBASSEMBLY #if V8_ENABLE_WEBASSEMBLY
...@@ -2738,8 +2704,8 @@ void InstructionSelector::VisitI8x16Shuffle(Node* node) { ...@@ -2738,8 +2704,8 @@ void InstructionSelector::VisitI8x16Shuffle(Node* node) {
? max_index - current_index ? max_index - current_index
: total_lane_count - current_index + max_index); : total_lane_count - current_index + max_index);
} }
Emit(kS390_I8x16Shuffle, g.DefineAsRegister(node), Emit(kS390_I8x16Shuffle, g.DefineAsRegister(node), g.UseRegister(input0),
g.UseUniqueRegister(input0), g.UseUniqueRegister(input1), g.UseRegister(input1),
g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped)), g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped)),
g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 4)), g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 4)),
g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 8)), g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 8)),
...@@ -2749,14 +2715,6 @@ void InstructionSelector::VisitI8x16Shuffle(Node* node) { ...@@ -2749,14 +2715,6 @@ void InstructionSelector::VisitI8x16Shuffle(Node* node) {
void InstructionSelector::VisitI8x16Shuffle(Node* node) { UNREACHABLE(); } void InstructionSelector::VisitI8x16Shuffle(Node* node) { UNREACHABLE(); }
#endif // V8_ENABLE_WEBASSEMBLY #endif // V8_ENABLE_WEBASSEMBLY
void InstructionSelector::VisitI8x16Swizzle(Node* node) {
S390OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kS390_I8x16Swizzle, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
}
// This is a replica of SimdShuffle::Pack4Lanes. However, above function will // This is a replica of SimdShuffle::Pack4Lanes. However, above function will
// not be available on builds with webassembly disabled, hence we need to have // not be available on builds with webassembly disabled, hence we need to have
// it declared locally as it is used on other visitors such as S128Const. // it declared locally as it is used on other visitors such as S128Const.
...@@ -2785,7 +2743,7 @@ void InstructionSelector::VisitS128Const(Node* node) { ...@@ -2785,7 +2743,7 @@ void InstructionSelector::VisitS128Const(Node* node) {
} else { } else {
// We have to use Pack4Lanes to reverse the bytes (lanes) on BE, // We have to use Pack4Lanes to reverse the bytes (lanes) on BE,
// Which in this case is ineffective on LE. // Which in this case is ineffective on LE.
Emit(kS390_S128Const, g.DefineAsRegister(node), Emit(kS390_S128Const, dst,
g.UseImmediate(Pack4Lanes(bit_cast<uint8_t*>(&val[0]))), g.UseImmediate(Pack4Lanes(bit_cast<uint8_t*>(&val[0]))),
g.UseImmediate(Pack4Lanes(bit_cast<uint8_t*>(&val[0]) + 4)), g.UseImmediate(Pack4Lanes(bit_cast<uint8_t*>(&val[0]) + 4)),
g.UseImmediate(Pack4Lanes(bit_cast<uint8_t*>(&val[0]) + 8)), g.UseImmediate(Pack4Lanes(bit_cast<uint8_t*>(&val[0]) + 8)),
......
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