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Commit 1d735a2d authored by dusan.m.milosavljevic's avatar dusan.m.milosavljevic Committed by Commit bot
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MIPS: [turbofan] Enable Word32 safe shifts. 

TEST=
BUG=

Review URL: https://codereview.chromium.org/1483973002

Cr-Commit-Position: refs/heads/master@{#32465}
parent 79ded5ac
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Showing with 16 additions and 14 deletions
src/compiler/mips/instruction-selector-mips.cc
View file @ 1d735a2d
...@@ -1200,7 +1200,8 @@ InstructionSelector::SupportedMachineOperatorFlags() { ...@@ -1200,7 +1200,8 @@ InstructionSelector::SupportedMachineOperatorFlags() {
MachineOperatorBuilder::kFloat64RoundTruncate | MachineOperatorBuilder::kFloat64RoundTruncate |
MachineOperatorBuilder::kFloat64RoundTiesEven; MachineOperatorBuilder::kFloat64RoundTiesEven;
} }
return flags | MachineOperatorBuilder::kFloat64Min | return flags | MachineOperatorBuilder::kWord32ShiftIsSafe |
MachineOperatorBuilder::kFloat64Min |
MachineOperatorBuilder::kFloat64Max | MachineOperatorBuilder::kFloat64Max |
MachineOperatorBuilder::kFloat32Min | MachineOperatorBuilder::kFloat32Min |
MachineOperatorBuilder::kFloat32Max | MachineOperatorBuilder::kFloat32Max |
......
src/compiler/mips64/instruction-selector-mips64.cc
View file @ 1d735a2d
...@@ -1611,7 +1611,8 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) { ...@@ -1611,7 +1611,8 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
// static // static
MachineOperatorBuilder::Flags MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() { InstructionSelector::SupportedMachineOperatorFlags() {
return MachineOperatorBuilder::kFloat64Min | return MachineOperatorBuilder::kWord32ShiftIsSafe |
MachineOperatorBuilder::kFloat64Min |
MachineOperatorBuilder::kFloat64Max | MachineOperatorBuilder::kFloat64Max |
MachineOperatorBuilder::kFloat32Min | MachineOperatorBuilder::kFloat32Min |
MachineOperatorBuilder::kFloat32Max | MachineOperatorBuilder::kFloat32Max |
......
src/mips/assembler-mips.cc
View file @ 1d735a2d
...@@ -1653,7 +1653,7 @@ void Assembler::sll(Register rd, ...@@ -1653,7 +1653,7 @@ void Assembler::sll(Register rd,
// nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
// instructions. // instructions.
DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
} }
...@@ -1663,7 +1663,7 @@ void Assembler::sllv(Register rd, Register rt, Register rs) { ...@@ -1663,7 +1663,7 @@ void Assembler::sllv(Register rd, Register rt, Register rs) {
void Assembler::srl(Register rd, Register rt, uint16_t sa) { void Assembler::srl(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
} }
...@@ -1673,7 +1673,7 @@ void Assembler::srlv(Register rd, Register rt, Register rs) { ...@@ -1673,7 +1673,7 @@ void Assembler::srlv(Register rd, Register rt, Register rs) {
void Assembler::sra(Register rd, Register rt, uint16_t sa) { void Assembler::sra(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
} }
......
src/mips64/assembler-mips64.cc
View file @ 1d735a2d
...@@ -1716,7 +1716,7 @@ void Assembler::sll(Register rd, ...@@ -1716,7 +1716,7 @@ void Assembler::sll(Register rd,
// nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
// instructions. // instructions.
DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
} }
...@@ -1726,7 +1726,7 @@ void Assembler::sllv(Register rd, Register rt, Register rs) { ...@@ -1726,7 +1726,7 @@ void Assembler::sllv(Register rd, Register rt, Register rs) {
void Assembler::srl(Register rd, Register rt, uint16_t sa) { void Assembler::srl(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
} }
...@@ -1736,7 +1736,7 @@ void Assembler::srlv(Register rd, Register rt, Register rs) { ...@@ -1736,7 +1736,7 @@ void Assembler::srlv(Register rd, Register rt, Register rs) {
void Assembler::sra(Register rd, Register rt, uint16_t sa) { void Assembler::sra(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
} }
...@@ -1766,7 +1766,7 @@ void Assembler::rotrv(Register rd, Register rt, Register rs) { ...@@ -1766,7 +1766,7 @@ void Assembler::rotrv(Register rd, Register rt, Register rs) {
void Assembler::dsll(Register rd, Register rt, uint16_t sa) { void Assembler::dsll(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL);
} }
...@@ -1776,7 +1776,7 @@ void Assembler::dsllv(Register rd, Register rt, Register rs) { ...@@ -1776,7 +1776,7 @@ void Assembler::dsllv(Register rd, Register rt, Register rs) {
void Assembler::dsrl(Register rd, Register rt, uint16_t sa) { void Assembler::dsrl(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL);
} }
...@@ -1802,7 +1802,7 @@ void Assembler::drotrv(Register rd, Register rt, Register rs) { ...@@ -1802,7 +1802,7 @@ void Assembler::drotrv(Register rd, Register rt, Register rs) {
void Assembler::dsra(Register rd, Register rt, uint16_t sa) { void Assembler::dsra(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA);
} }
...@@ -1812,17 +1812,17 @@ void Assembler::dsrav(Register rd, Register rt, Register rs) { ...@@ -1812,17 +1812,17 @@ void Assembler::dsrav(Register rd, Register rt, Register rs) {
void Assembler::dsll32(Register rd, Register rt, uint16_t sa) { void Assembler::dsll32(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL32); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL32);
} }
void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) { void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL32); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL32);
} }
void Assembler::dsra32(Register rd, Register rt, uint16_t sa) { void Assembler::dsra32(Register rd, Register rt, uint16_t sa) {
GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA32); GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA32);
} }
......
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