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Commit 1cb5974e authored by Junliang Yan's avatar Junliang Yan Committed by Commit Bot
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s390x: cleanup Pair Ops 

Pair Ops are for 31-bit support.
We had drop 31-bit support long time ago so don't need them anymore.

Change-Id: Iff1f8df19433fd1431316888d0c5276b9710b1fc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2576003
Commit-Queue: Junliang Yan <junyan@redhat.com>
Reviewed-by: 's avatarMilad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71625}
parent 1d7aa2f8
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src/codegen/s390/macro-assembler-s390.cc
View file @ 1cb5974e
......@@ -1223,68 +1223,6 @@ void TurboAssembler::ConvertDoubleToUnsignedInt32(
clfdbr(m, Condition(0), dst, double_input);
}
#if !V8_TARGET_ARCH_S390X
void TurboAssembler::ShiftLeftPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
Register scratch, Register shift) {
LoadRR(r0, src_high);
LoadRR(r1, src_low);
sldl(r0, shift, Operand::Zero());
LoadRR(dst_high, r0);
LoadRR(dst_low, r1);
}
void TurboAssembler::ShiftLeftPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
uint32_t shift) {
LoadRR(r0, src_high);
LoadRR(r1, src_low);
sldl(r0, r0, Operand(shift));
LoadRR(dst_high, r0);
LoadRR(dst_low, r1);
}
void TurboAssembler::ShiftRightPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
Register scratch, Register shift) {
LoadRR(r0, src_high);
LoadRR(r1, src_low);
srdl(r0, shift, Operand::Zero());
LoadRR(dst_high, r0);
LoadRR(dst_low, r1);
}
void TurboAssembler::ShiftRightPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
uint32_t shift) {
LoadRR(r0, src_high);
LoadRR(r1, src_low);
srdl(r0, Operand(shift));
LoadRR(dst_high, r0);
LoadRR(dst_low, r1);
}
void TurboAssembler::ShiftRightArithPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
Register scratch, Register shift) {
LoadRR(r0, src_high);
LoadRR(r1, src_low);
srda(r0, shift, Operand::Zero());
LoadRR(dst_high, r0);
LoadRR(dst_low, r1);
}
void TurboAssembler::ShiftRightArithPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
uint32_t shift) {
LoadRR(r0, src_high);
LoadRR(r1, src_low);
srda(r0, r0, Operand(shift));
LoadRR(dst_high, r0);
LoadRR(dst_low, r1);
}
#endif
void TurboAssembler::MovDoubleToInt64(Register dst, DoubleRegister src) {
lgdr(dst, src);
}
......@@ -2721,12 +2659,6 @@ void TurboAssembler::Add32(Register dst, const Operand& opnd) {
afi(dst, opnd);
}
// Add 32-bit (Register dst = Register dst + Immediate opnd)
void TurboAssembler::Add32_RI(Register dst, const Operand& opnd) {
// Just a wrapper for above
Add32(dst, opnd);
}
// Add Pointer Size (Register dst = Register dst + Immediate opnd)
void TurboAssembler::AddP(Register dst, const Operand& opnd) {
#if V8_TARGET_ARCH_S390X
......@@ -2751,13 +2683,6 @@ void TurboAssembler::Add32(Register dst, Register src, const Operand& opnd) {
Add32(dst, opnd);
}
// Add 32-bit (Register dst = Register src + Immediate opnd)
void TurboAssembler::Add32_RRI(Register dst, Register src,
const Operand& opnd) {
// Just a wrapper for above
Add32(dst, src, opnd);
}
// Add Pointer Size (Register dst = Register src + Immediate opnd)
void TurboAssembler::AddP(Register dst, Register src, const Operand& opnd) {
if (dst != src) {
......@@ -2899,23 +2824,6 @@ void TurboAssembler::AddP(const MemOperand& opnd, const Operand& imm) {
// Add Logical Instructions
//----------------------------------------------------------------------------
// Add Logical With Carry 32-bit (Register dst = Register src1 + Register src2)
void TurboAssembler::AddLogicalWithCarry32(Register dst, Register src1,
Register src2) {
if (dst != src2 && dst != src1) {
lr(dst, src1);
alcr(dst, src2);
} else if (dst != src2) {
// dst == src1
DCHECK(dst == src1);
alcr(dst, src2);
} else {
// dst == src2
DCHECK(dst == src2);
alcr(dst, src1);
}
}
// Add Logical 32-bit (Register dst = Register src1 + Register src2)
void TurboAssembler::AddLogical32(Register dst, Register src1, Register src2) {
if (dst != src2 && dst != src1) {
......
src/codegen/s390/macro-assembler-s390.h
View file @ 1cb5974e
......@@ -260,10 +260,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
// Add (Register - Immediate)
void Add32(Register dst, const Operand& imm);
void Add32_RI(Register dst, const Operand& imm);
void AddP(Register dst, const Operand& imm);
void Add32(Register dst, Register src, const Operand& imm);
void Add32_RRI(Register dst, Register src, const Operand& imm);
void AddP(Register dst, Register src, const Operand& imm);
// Add (Register - Register)
......@@ -726,22 +724,6 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
const Register result, const DoubleRegister double_input,
FPRoundingMode rounding_mode = kRoundToZero);
#if !V8_TARGET_ARCH_S390X
void ShiftLeftPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, Register scratch, Register shift);
void ShiftLeftPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, uint32_t shift);
void ShiftRightPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, Register scratch, Register shift);
void ShiftRightPair(Register dst_low, Register dst_high, Register src_low,
Register src_high, uint32_t shift);
void ShiftRightArithPair(Register dst_low, Register dst_high,
Register src_low, Register src_high,
Register scratch, Register shift);
void ShiftRightArithPair(Register dst_low, Register dst_high,
Register src_low, Register src_high, uint32_t shift);
#endif
// Generates function and stub prologue code.
void StubPrologue(StackFrame::Type type, Register base = no_reg,
int prologue_offset = 0);
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ 1cb5974e
......@@ -1598,81 +1598,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_ShiftRightArith64:
ASSEMBLE_BIN_OP(RRRInstr(srag), nullInstr, RRIInstr(srag));
break;
#if !V8_TARGET_ARCH_S390X
case kS390_AddPair:
// i.InputRegister(0) ... left low word.
// i.InputRegister(1) ... left high word.
// i.InputRegister(2) ... right low word.
// i.InputRegister(3) ... right high word.
__ AddLogical32(i.OutputRegister(0), i.InputRegister(0),
i.InputRegister(2));
__ AddLogicalWithCarry32(i.OutputRegister(1), i.InputRegister(1),
i.InputRegister(3));
break;
case kS390_SubPair:
// i.InputRegister(0) ... left low word.
// i.InputRegister(1) ... left high word.
// i.InputRegister(2) ... right low word.
// i.InputRegister(3) ... right high word.
__ SubLogical32(i.OutputRegister(0), i.InputRegister(0),
i.InputRegister(2));
__ SubLogicalWithBorrow32(i.OutputRegister(1), i.InputRegister(1),
i.InputRegister(3));
break;
case kS390_MulPair:
// i.InputRegister(0) ... left low word.
// i.InputRegister(1) ... left high word.
// i.InputRegister(2) ... right low word.
// i.InputRegister(3) ... right high word.
__ sllg(r0, i.InputRegister(1), Operand(32));
__ sllg(r1, i.InputRegister(3), Operand(32));
__ lr(r0, i.InputRegister(0));
__ lr(r1, i.InputRegister(2));
__ msgr(r1, r0);
__ lr(i.OutputRegister(0), r1);
__ srag(i.OutputRegister(1), r1, Operand(32));
break;
case kS390_ShiftLeftPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftLeftPair(i.OutputRegister(0), second_output, i.InputRegister(0),
i.InputRegister(1), i.InputInt32(2));
} else {
__ ShiftLeftPair(i.OutputRegister(0), second_output, i.InputRegister(0),
i.InputRegister(1), kScratchReg, i.InputRegister(2));
}
break;
}
case kS390_ShiftRightPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2));
}
break;
}
case kS390_ShiftRightArithPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightArithPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightArithPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
kScratchReg, i.InputRegister(2));
}
break;
}
#endif
case kS390_RotRight32: {
// zero-ext
if (HasRegisterInput(instr, 1)) {
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ 1cb5974e
......@@ -1054,114 +1054,6 @@ static inline bool TryMatchSignExtInt16OrInt8FromWord32Sar(
return false;
}
#if !V8_TARGET_ARCH_S390X
void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
InstructionCode opcode2, Node* node) {
S390OperandGenerator g(selector);
Node* projection1 = NodeProperties::FindProjection(node, 1);
if (projection1) {
// We use UseUniqueRegister here to avoid register sharing with the output
// registers.
InstructionOperand inputs[] = {
g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))};
InstructionOperand outputs[] = {
g.DefineAsRegister(node),
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
selector->Emit(opcode, 2, outputs, 4, inputs);
} else {
// The high word of the result is not used, so we emit the standard 32 bit
// instruction.
selector->Emit(opcode2, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(2)), g.TempImmediate(0));
}
}
void InstructionSelector::VisitInt32PairAdd(Node* node) {
VisitPairBinop(this, kS390_AddPair, kS390_Add32, node);
}
void InstructionSelector::VisitInt32PairSub(Node* node) {
VisitPairBinop(this, kS390_SubPair, kS390_Sub32, node);
}
void InstructionSelector::VisitInt32PairMul(Node* node) {
S390OperandGenerator g(this);
Node* projection1 = NodeProperties::FindProjection(node, 1);
if (projection1) {
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
g.UseUniqueRegister(node->InputAt(2)),
g.UseUniqueRegister(node->InputAt(3))};
InstructionOperand outputs[] = {
g.DefineAsRegister(node),
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
Emit(kS390_MulPair, 2, outputs, 4, inputs);
} else {
// The high word of the result is not used, so we emit the standard 32 bit
// instruction.
Emit(kS390_Mul32, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(2)),
g.TempImmediate(0));
}
}
namespace {
// Shared routine for multiple shift operations.
void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
Node* node) {
S390OperandGenerator g(selector);
// We use g.UseUniqueRegister here to guarantee that there is
// no register aliasing of input registers with output registers.
Int32Matcher m(node->InputAt(2));
InstructionOperand shift_operand;
if (m.HasResolvedValue()) {
shift_operand = g.UseImmediate(m.node());
} else {
shift_operand = g.UseUniqueRegister(m.node());
}
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
shift_operand};
Node* projection1 = NodeProperties::FindProjection(node, 1);
InstructionOperand outputs[2];
InstructionOperand temps[1];
int32_t output_count = 0;
int32_t temp_count = 0;
outputs[output_count++] = g.DefineAsRegister(node);
if (projection1) {
outputs[output_count++] = g.DefineAsRegister(projection1);
} else {
temps[temp_count++] = g.TempRegister();
}
selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps);
}
} // namespace
void InstructionSelector::VisitWord32PairShl(Node* node) {
VisitPairShift(this, kS390_ShiftLeftPair, node);
}
void InstructionSelector::VisitWord32PairShr(Node* node) {
VisitPairShift(this, kS390_ShiftRightPair, node);
}
void InstructionSelector::VisitWord32PairSar(Node* node) {
VisitPairShift(this, kS390_ShiftRightArithPair, node);
}
#endif
void InstructionSelector::VisitWord32Rol(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitWord64Rol(Node* node) { UNREACHABLE(); }
......
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