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Commit 1bb1d634 authored by Zhao Jiazhong's avatar Zhao Jiazhong Committed by Commit Bot
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[mips][wasm-simd][liftoff] Implement min of i8x16, i16x8, i32x4 

Port ec4ccade
https://crrev.com/c/2129176

Change-Id: I6c37c6a2be4a42c440dd8c0920647a587f55e44d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2135546Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#66980}
parent e8ff83dd
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src/wasm/baseline/mips/liftoff-assembler-mips.h
View file @ 1bb1d634
......@@ -1736,6 +1736,24 @@ void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs,
bailout(kSimd, "emit_i32x4_mul");
}
void LiftoffAssembler::emit_i32x4_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i32x4_min_s");
}
void LiftoffAssembler::emit_i32x4_min_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i32x4_min_u");
}
void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1814,6 +1832,24 @@ void LiftoffAssembler::emit_i16x8_add_saturate_u(LiftoffRegister dst,
bailout(kSimd, "emit_i16x8_add_saturate_u");
}
void LiftoffAssembler::emit_i16x8_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i16x8_min_s");
}
void LiftoffAssembler::emit_i16x8_min_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i16x8_min_u");
}
void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1892,6 +1928,24 @@ void LiftoffAssembler::emit_i8x16_add_saturate_u(LiftoffRegister dst,
bailout(kSimd, "emit_i8x16_add_saturate_u");
}
void LiftoffAssembler::emit_i8x16_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i8x16_min_s");
}
void LiftoffAssembler::emit_i8x16_min_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i8x16_min_u");
}
void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) {
TurboAssembler::Ulw(limit_address, MemOperand(limit_address));
TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address));
......
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
View file @ 1bb1d634
......@@ -1528,6 +1528,24 @@ void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs,
bailout(kSimd, "emit_i32x4_mul");
}
void LiftoffAssembler::emit_i32x4_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i32x4_min_s");
}
void LiftoffAssembler::emit_i32x4_min_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i32x4_min_u");
}
void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1606,6 +1624,24 @@ void LiftoffAssembler::emit_i16x8_add_saturate_u(LiftoffRegister dst,
bailout(kSimd, "emit_i16x8_add_saturate_u");
}
void LiftoffAssembler::emit_i16x8_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i16x8_min_s");
}
void LiftoffAssembler::emit_i16x8_min_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i16x8_min_u");
}
void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1684,6 +1720,24 @@ void LiftoffAssembler::emit_i8x16_add_saturate_u(LiftoffRegister dst,
bailout(kSimd, "emit_i8x16_add_saturate_u");
}
void LiftoffAssembler::emit_i8x16_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i8x16_min_s");
}
void LiftoffAssembler::emit_i8x16_min_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i8x16_min_u");
}
void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) {
TurboAssembler::Uld(limit_address, MemOperand(limit_address));
TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address));
......
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