ppc: [liftoff] implement shift operations

Change-Id: I61d07f61a344422a2048530a0497a2dc1a17b640
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3038252Reviewed-by: Milad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75794}

src/codegen/ppc/macro-assembler-ppc.cc

@@ -2810,6 +2810,66 @@ void TurboAssembler::XorU32(Register dst, Register src, Register value,
   extsw(dst, dst, r);
 }
 
+void TurboAssembler::ShiftLeftU64(Register dst, Register src,
+                                  const Operand& value, RCBit r) {
+  sldi(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightU64(Register dst, Register src,
+                                   const Operand& value, RCBit r) {
+  srdi(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightS64(Register dst, Register src,
+                                   const Operand& value, RCBit r) {
+  sradi(dst, src, value.immediate(), r);
+}
+
+void TurboAssembler::ShiftLeftU32(Register dst, Register src,
+                                  const Operand& value, RCBit r) {
+  slwi(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightU32(Register dst, Register src,
+                                   const Operand& value, RCBit r) {
+  srwi(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightS32(Register dst, Register src,
+                                   const Operand& value, RCBit r) {
+  srawi(dst, src, value.immediate(), r);
+}
+
+void TurboAssembler::ShiftLeftU64(Register dst, Register src, Register value,
+                                  RCBit r) {
+  sld(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightU64(Register dst, Register src, Register value,
+                                   RCBit r) {
+  srd(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightS64(Register dst, Register src, Register value,
+                                   RCBit r) {
+  srad(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftLeftU32(Register dst, Register src, Register value,
+                                  RCBit r) {
+  slw(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightU32(Register dst, Register src, Register value,
+                                   RCBit r) {
+  srw(dst, src, value, r);
+}
+
+void TurboAssembler::ShiftRightS32(Register dst, Register src, Register value,
+                                   RCBit r) {
+  sraw(dst, src, value, r);
+}
+
 void TurboAssembler::CmpS64(Register src1, Register src2, CRegister cr) {
   cmp(src1, src2, cr);
 }

src/codegen/ppc/macro-assembler-ppc.h

@@ -217,6 +217,31 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
               Register scratch = r0, RCBit r = SetRC);
   void XorU32(Register dst, Register src, Register value, RCBit r = LeaveRC);
 
+  void ShiftLeftU64(Register dst, Register src, const Operand& value,
+                    RCBit r = LeaveRC);
+  void ShiftRightU64(Register dst, Register src, const Operand& value,
+                     RCBit r = LeaveRC);
+  void ShiftRightS64(Register dst, Register src, const Operand& value,
+                     RCBit r = LeaveRC);
+  void ShiftLeftU32(Register dst, Register src, const Operand& value,
+                    RCBit r = LeaveRC);
+  void ShiftRightU32(Register dst, Register src, const Operand& value,
+                     RCBit r = LeaveRC);
+  void ShiftRightS32(Register dst, Register src, const Operand& value,
+                     RCBit r = LeaveRC);
+  void ShiftLeftU64(Register dst, Register src, Register value,
+                    RCBit r = LeaveRC);
+  void ShiftRightU64(Register dst, Register src, Register value,
+                     RCBit r = LeaveRC);
+  void ShiftRightS64(Register dst, Register src, Register value,
+                     RCBit r = LeaveRC);
+  void ShiftLeftU32(Register dst, Register src, Register value,
+                    RCBit r = LeaveRC);
+  void ShiftRightU32(Register dst, Register src, Register value,
+                     RCBit r = LeaveRC);
+  void ShiftRightS32(Register dst, Register src, Register value,
+                     RCBit r = LeaveRC);
+
   void Push(Register src) { push(src); }
   // Push a handle.
   void Push(Handle<HeapObject> handle);

src/wasm/baseline/ppc/liftoff-assembler-ppc.h

@@ -784,13 +784,7 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
   }
 
 UNIMPLEMENTED_I32_BINOP(i32_mul)
-UNIMPLEMENTED_I32_SHIFTOP(i32_shl)
-UNIMPLEMENTED_I32_SHIFTOP(i32_sar)
-UNIMPLEMENTED_I32_SHIFTOP(i32_shr)
 UNIMPLEMENTED_I64_BINOP(i64_mul)
-UNIMPLEMENTED_I64_SHIFTOP(i64_shl)
-UNIMPLEMENTED_I64_SHIFTOP(i64_sar)
-UNIMPLEMENTED_I64_SHIFTOP(i64_shr)
 UNIMPLEMENTED_GP_UNOP(i32_clz)
 UNIMPLEMENTED_GP_UNOP(i32_ctz)
 UNIMPLEMENTED_FP_BINOP(f32_add)
@@ -899,7 +893,31 @@ UNOP_LIST(EMIT_UNOP_FUNCTION)
   V(i64_ori, OrU64, LiftoffRegister, LiftoffRegister, int32_t, LFR_TO_REG,   \
     LFR_TO_REG, Operand, USE, , void)                                        \
   V(i64_xori, XorU64, LiftoffRegister, LiftoffRegister, int32_t, LFR_TO_REG, \
-    LFR_TO_REG, Operand, USE, , void)
+    LFR_TO_REG, Operand, USE, , void)                                        \
+  V(i32_shli, ShiftLeftU32, Register, Register, int32_t, , ,                 \
+    INT32_AND_WITH_1F, USE, , void)                                          \
+  V(i32_sari, ShiftRightS32, Register, Register, int32_t, , ,                \
+    INT32_AND_WITH_1F, USE, , void)                                          \
+  V(i32_shri, ShiftRightU32, Register, Register, int32_t, , ,                \
+    INT32_AND_WITH_1F, USE, , void)                                          \
+  V(i32_shl, ShiftLeftU32, Register, Register, Register, , ,                 \
+    REGISTER_AND_WITH_1F, USE, , void)                                       \
+  V(i32_sar, ShiftRightS32, Register, Register, Register, , ,                \
+    REGISTER_AND_WITH_1F, USE, , void)                                       \
+  V(i32_shr, ShiftRightU32, Register, Register, Register, , ,                \
+    REGISTER_AND_WITH_1F, USE, , void)                                       \
+  V(i64_shl, ShiftLeftU64, LiftoffRegister, LiftoffRegister, Register,       \
+    LFR_TO_REG, LFR_TO_REG, , USE, , void)                                   \
+  V(i64_sar, ShiftRightS64, LiftoffRegister, LiftoffRegister, Register,      \
+    LFR_TO_REG, LFR_TO_REG, , USE, , void)                                   \
+  V(i64_shr, ShiftRightU64, LiftoffRegister, LiftoffRegister, Register,      \
+    LFR_TO_REG, LFR_TO_REG, , USE, , void)                                   \
+  V(i64_shli, ShiftLeftU64, LiftoffRegister, LiftoffRegister, int32_t,       \
+    LFR_TO_REG, LFR_TO_REG, Operand, USE, , void)                            \
+  V(i64_sari, ShiftRightS64, LiftoffRegister, LiftoffRegister, int32_t,      \
+    LFR_TO_REG, LFR_TO_REG, Operand, USE, , void)                            \
+  V(i64_shri, ShiftRightU64, LiftoffRegister, LiftoffRegister, int32_t,      \
+    LFR_TO_REG, LFR_TO_REG, Operand, USE, , void)
 
 #define EMIT_BINOP_FUNCTION(name, instr, dtype, stype1, stype2, dcast, scast1, \
                             scast2, rcast, ret, return_type)                   \