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Commit 1905c05c authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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PPC: [wasm-simd] Add to simd conversion operations 

Change-Id: I96b8b6735b4a1d8bb42040ecd9e46c5e97675749
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2298141Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68870}
parent 2a08e065
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Showing with 161 additions and 97 deletions
src/codegen/ppc/assembler-ppc.h
View file @ 1905c05c
......@@ -474,6 +474,10 @@ class Assembler : public AssemblerBase {
const Simd128Register rb) { \
vx_form(instr_name, rt, ra, rb); \
}
#define DECLARE_PPC_VX_INSTRUCTIONS_C_FORM(name, instr_name, instr_value) \
inline void name(const Simd128Register rt, const Simd128Register rb) { \
vx_form(instr_name, rt, rb); \
}
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb,
const Operand& imm) {
......@@ -483,11 +487,16 @@ class Assembler : public AssemblerBase {
Simd128Register rb) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb) {
emit(instr | rt.code() * B21 | rb.code() * B11);
}
PPC_VX_OPCODE_A_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_A_FORM)
PPC_VX_OPCODE_B_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_B_FORM)
PPC_VX_OPCODE_C_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_C_FORM)
#undef DECLARE_PPC_VX_INSTRUCTIONS_A_FORM
#undef DECLARE_PPC_VX_INSTRUCTIONS_B_FORM
#undef DECLARE_PPC_VX_INSTRUCTIONS_C_FORM
#define DECLARE_PPC_VA_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \
inline void name(const Simd128Register rt, const Simd128Register ra, \
......
src/codegen/ppc/constants-ppc.h
View file @ 1905c05c
......@@ -2314,7 +2314,25 @@ using Instr = uint32_t;
/* Vector Shift Right Algebraic Doubleword */ \
V(vsrad, VSRAD, 0x100003C4) \
/* Vector Logical AND */ \
V(vand, VAND, 0x10000404)
V(vand, VAND, 0x10000404) \
/* Vector Pack Signed Word Signed Saturate */ \
V(vpkswss, VPKSWSS, 0x100001CE) \
/* Vector Pack Signed Word Unsigned Saturate */ \
V(vpkswus, VPKSWUS, 0x1000014E) \
/* Vector Pack Signed Halfword Signed Saturate */ \
V(vpkshss, VPKSHSS, 0x1000018E) \
/* Vector Pack Signed Halfword Unsigned Saturate */ \
V(vpkshus, VPKSHUS, 0x1000010E)
#define PPC_VX_OPCODE_C_FORM_LIST(V) \
/* Vector Unpack Low Signed Halfword */ \
V(vupklsh, VUPKLSH, 0x100002CE) \
/* Vector Unpack High Signed Halfword */ \
V(vupkhsh, VUPKHSH, 0x1000024E) \
/* Vector Unpack Low Signed Byte */ \
V(vupklsb, VUPKLSB, 0x1000028E) \
/* Vector Unpack High Signed Byte */ \
V(vupkhsb, VUPKHSB, 0x1000020E)
#define PPC_VX_OPCODE_UNUSED_LIST(V) \
/* Decimal Add Modulo */ \
......@@ -2431,14 +2449,6 @@ using Instr = uint32_t;
V(vpksdss, VPKSDSS, 0x100005CE) \
/* Vector Pack Signed Doubleword Unsigned Saturate */ \
V(vpksdus, VPKSDUS, 0x1000054E) \
/* Vector Pack Signed Halfword Signed Saturate */ \
V(vpkshss, VPKSHSS, 0x1000018E) \
/* Vector Pack Signed Halfword Unsigned Saturate */ \
V(vpkshus, VPKSHUS, 0x1000010E) \
/* Vector Pack Signed Word Signed Saturate */ \
V(vpkswss, VPKSWSS, 0x100001CE) \
/* Vector Pack Signed Word Unsigned Saturate */ \
V(vpkswus, VPKSWUS, 0x1000014E) \
/* Vector Pack Unsigned Doubleword Unsigned Saturate */ \
V(vpkudus, VPKUDUS, 0x100004CE) \
/* Vector Pack Unsigned Halfword Unsigned Saturate */ \
......@@ -2517,18 +2527,10 @@ using Instr = uint32_t;
V(vsumsws, VSUMSWS, 0x10000788) \
/* Vector Unpack High Pixel */ \
V(vupkhpx, VUPKHPX, 0x1000034E) \
/* Vector Unpack High Signed Byte */ \
V(vupkhsb, VUPKHSB, 0x1000020E) \
/* Vector Unpack High Signed Halfword */ \
V(vupkhsh, VUPKHSH, 0x1000024E) \
/* Vector Unpack High Signed Word */ \
V(vupkhsw, VUPKHSW, 0x1000064E) \
/* Vector Unpack Low Pixel */ \
V(vupklpx, VUPKLPX, 0x100003CE) \
/* Vector Unpack Low Signed Byte */ \
V(vupklsb, VUPKLSB, 0x1000028E) \
/* Vector Unpack Low Signed Halfword */ \
V(vupklsh, VUPKLSH, 0x100002CE) \
/* Vector Unpack Low Signed Word */ \
V(vupklsw, VUPKLSW, 0x100006CE) \
/* Vector AES Cipher */ \
......@@ -2553,6 +2555,7 @@ using Instr = uint32_t;
#define PPC_VX_OPCODE_LIST(V) \
PPC_VX_OPCODE_A_FORM_LIST(V) \
PPC_VX_OPCODE_B_FORM_LIST(V) \
PPC_VX_OPCODE_C_FORM_LIST(V) \
PPC_VX_OPCODE_UNUSED_LIST(V)
#define PPC_XS_OPCODE_LIST(V) \
......
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ 1905c05c
......@@ -3072,14 +3072,89 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kPPC_F32x4SConvertI32x4: {
__ xvcvsxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4UConvertI32x4: {
__ xvcvuxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I32x4SConvertI16x8Low: {
__ vupklsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I32x4SConvertI16x8High: {
__ vupkhsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I32x4UConvertI16x8Low: {
__ vupklsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
// Zero extend.
__ mov(ip, Operand(0xFFFF));
__ mtvsrd(kScratchDoubleReg, ip);
__ vspltw(kScratchDoubleReg, kScratchDoubleReg, Operand(1));
__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
i.OutputSimd128Register());
break;
}
case kPPC_I32x4UConvertI16x8High: {
__ vupkhsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
// Zero extend.
__ mov(ip, Operand(0xFFFF));
__ mtvsrd(kScratchDoubleReg, ip);
__ vspltw(kScratchDoubleReg, kScratchDoubleReg, Operand(1));
__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
i.OutputSimd128Register());
break;
}
case kPPC_I16x8SConvertI8x16Low: {
__ vupklsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I16x8SConvertI8x16High: {
__ vupkhsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I16x8UConvertI8x16Low: {
__ vupklsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
// Zero extend.
__ li(ip, Operand(0xFF));
__ mtvsrd(kScratchDoubleReg, ip);
__ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3));
__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
i.OutputSimd128Register());
break;
}
case kPPC_I16x8UConvertI8x16High: {
__ vupkhsb(i.OutputSimd128Register(), i.InputSimd128Register(0));
// Zero extend.
__ li(ip, Operand(0xFF));
__ mtvsrd(kScratchDoubleReg, ip);
__ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3));
__ vand(i.OutputSimd128Register(), kScratchDoubleReg,
i.OutputSimd128Register());
break;
}
case kPPC_I16x8SConvertI32x4: {
__ vpkswss(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8UConvertI32x4: {
__ vpkswus(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16SConvertI16x8: {
__ vpkshss(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16UConvertI16x8: {
__ vpkshus(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break;
......
src/compiler/backend/ppc/instruction-codes-ppc.h
View file @ 1905c05c
......@@ -265,6 +265,10 @@ namespace compiler {
V(PPC_I32x4Abs) \
V(PPC_I32x4SConvertF32x4) \
V(PPC_I32x4UConvertF32x4) \
V(PPC_I32x4SConvertI16x8Low) \
V(PPC_I32x4SConvertI16x8High) \
V(PPC_I32x4UConvertI16x8Low) \
V(PPC_I32x4UConvertI16x8High) \
V(PPC_I16x8Splat) \
V(PPC_I16x8ExtractLaneU) \
V(PPC_I16x8ExtractLaneS) \
......@@ -288,6 +292,12 @@ namespace compiler {
V(PPC_I16x8ShrU) \
V(PPC_I16x8Neg) \
V(PPC_I16x8Abs) \
V(PPC_I16x8SConvertI32x4) \
V(PPC_I16x8UConvertI32x4) \
V(PPC_I16x8SConvertI8x16Low) \
V(PPC_I16x8SConvertI8x16High) \
V(PPC_I16x8UConvertI8x16Low) \
V(PPC_I16x8UConvertI8x16High) \
V(PPC_I8x16Splat) \
V(PPC_I8x16ExtractLaneU) \
V(PPC_I8x16ExtractLaneS) \
......@@ -310,6 +320,8 @@ namespace compiler {
V(PPC_I8x16ShrU) \
V(PPC_I8x16Neg) \
V(PPC_I8x16Abs) \
V(PPC_I8x16SConvertI16x8) \
V(PPC_I8x16UConvertI16x8) \
V(PPC_V64x2AnyTrue) \
V(PPC_V32x4AnyTrue) \
V(PPC_V16x8AnyTrue) \
......
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
View file @ 1905c05c
......@@ -188,6 +188,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I32x4Abs:
case kPPC_I32x4SConvertF32x4:
case kPPC_I32x4UConvertF32x4:
case kPPC_I32x4SConvertI16x8Low:
case kPPC_I32x4SConvertI16x8High:
case kPPC_I32x4UConvertI16x8Low:
case kPPC_I32x4UConvertI16x8High:
case kPPC_I16x8Splat:
case kPPC_I16x8ExtractLaneU:
case kPPC_I16x8ExtractLaneS:
......@@ -211,6 +215,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I16x8ShrU:
case kPPC_I16x8Neg:
case kPPC_I16x8Abs:
case kPPC_I16x8SConvertI32x4:
case kPPC_I16x8UConvertI32x4:
case kPPC_I16x8SConvertI8x16Low:
case kPPC_I16x8SConvertI8x16High:
case kPPC_I16x8UConvertI8x16Low:
case kPPC_I16x8UConvertI8x16High:
case kPPC_I8x16Splat:
case kPPC_I8x16ExtractLaneU:
case kPPC_I8x16ExtractLaneS:
......@@ -233,6 +243,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I8x16ShrU:
case kPPC_I8x16Neg:
case kPPC_I8x16Abs:
case kPPC_I8x16SConvertI16x8:
case kPPC_I8x16UConvertI16x8:
case kPPC_V64x2AnyTrue:
case kPPC_V32x4AnyTrue:
case kPPC_V16x8AnyTrue:
......
src/compiler/backend/ppc/instruction-selector-ppc.cc
View file @ 1905c05c
......@@ -2179,6 +2179,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8GeS) \
V(I16x8GtU) \
V(I16x8GeU) \
V(I16x8SConvertI32x4) \
V(I16x8UConvertI32x4) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Mul) \
......@@ -2192,26 +2194,40 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16GeS) \
V(I8x16GtU) \
V(I8x16GeU) \
V(I8x16SConvertI16x8) \
V(I8x16UConvertI16x8) \
V(S128And) \
V(S128Or) \
V(S128Xor)
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
V(F64x2Sqrt) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4RecipApprox) \
V(F32x4RecipSqrtApprox) \
V(F32x4Sqrt) \
V(I64x2Neg) \
V(I32x4Neg) \
V(I32x4Abs) \
V(I16x8Neg) \
V(I16x8Abs) \
V(I8x16Neg) \
V(I8x16Abs) \
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
V(F64x2Sqrt) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4RecipApprox) \
V(F32x4RecipSqrtApprox) \
V(F32x4Sqrt) \
V(F32x4SConvertI32x4) \
V(F32x4UConvertI32x4) \
V(I64x2Neg) \
V(I32x4Neg) \
V(I32x4Abs) \
V(I32x4SConvertF32x4) \
V(I32x4UConvertF32x4) \
V(I32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High) \
V(I32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High) \
V(I16x8Neg) \
V(I16x8Abs) \
V(I8x16Neg) \
V(I8x16Abs) \
V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High) \
V(S128Not)
#define SIMD_SHIFT_LIST(V) \
......@@ -2236,12 +2252,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(V16x8AllTrue) \
V(V8x16AllTrue)
#define SIMD_CONVERSION_LIST(V) \
V(I32x4SConvertF32x4) \
V(I32x4UConvertF32x4) \
V(F32x4SConvertI32x4) \
V(F32x4UConvertI32x4)
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
PPCOperandGenerator g(this); \
......@@ -2322,16 +2332,6 @@ SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
#undef SIMD_VISIT_BOOL
#undef SIMD_BOOL_LIST
#define SIMD_VISIT_CONVERSION(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0))); \
}
SIMD_CONVERSION_LIST(SIMD_VISIT_CONVERSION)
#undef SIMD_VISIT_CONVERSION
#undef SIMD_CONVERSION_LIST
#undef SIMD_TYPES
void InstructionSelector::VisitS128Zero(Node* node) {
......@@ -2419,53 +2419,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertI16x8High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4UConvertI16x8Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4UConvertI16x8High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8UConvertI8x16Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
......
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