[mips][wasm-simd] Use signed extract lane

port 9fcbb5e3 https://crrev.com/c/1873700

Original Commit Message:

  Replace unsigned extract lane followed by sign extend
  as added here https://chromium-review.googlesource.com/c/v8/v8/+/1846711
  with a signed extract lane for I8x16 and I16x8.

Change-Id: I46f9d3ed364f28289e23a635281ea0ef44865d1a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1947689
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65340}

src/compiler/backend/mips/code-generator-mips.cc

@@ -2310,7 +2310,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
       break;
     }
-    case kMipsI16x8ExtractLane: {
+    case kMipsI16x8ExtractLaneU: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ copy_u_h(i.OutputRegister(), i.InputSimd128Register(0),
+                  i.InputInt8(1));
+      break;
+    }
+    case kMipsI16x8ExtractLaneS: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ copy_s_h(i.OutputRegister(), i.InputSimd128Register(0),
                   i.InputInt8(1));
@@ -2459,7 +2465,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ fill_b(i.OutputSimd128Register(), i.InputRegister(0));
       break;
     }
-    case kMipsI8x16ExtractLane: {
+    case kMipsI8x16ExtractLaneU: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ copy_u_b(i.OutputRegister(), i.InputSimd128Register(0),
+                  i.InputInt8(1));
+      break;
+    }
+    case kMipsI8x16ExtractLaneS: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ copy_s_b(i.OutputRegister(), i.InputSimd128Register(0),
                   i.InputInt8(1));

src/compiler/backend/mips/instruction-codes-mips.h

@@ -201,7 +201,8 @@ namespace compiler {
   V(MipsI32x4GtU)                  \
   V(MipsI32x4GeU)                  \
   V(MipsI16x8Splat)                \
-  V(MipsI16x8ExtractLane)          \
+  V(MipsI16x8ExtractLaneU)         \
+  V(MipsI16x8ExtractLaneS)         \
   V(MipsI16x8ReplaceLane)          \
   V(MipsI16x8Neg)                  \
   V(MipsI16x8Shl)                  \
@@ -226,7 +227,8 @@ namespace compiler {
   V(MipsI16x8GtU)                  \
   V(MipsI16x8GeU)                  \
   V(MipsI8x16Splat)                \
-  V(MipsI8x16ExtractLane)          \
+  V(MipsI8x16ExtractLaneU)         \
+  V(MipsI8x16ExtractLaneS)         \
   V(MipsI8x16ReplaceLane)          \
   V(MipsI8x16Neg)                  \
   V(MipsI8x16Shl)                  \

src/compiler/backend/mips/instruction-scheduler-mips.cc

@@ -106,7 +106,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsI16x8AddSaturateS:
     case kMipsI16x8AddSaturateU:
     case kMipsI16x8Eq:
-    case kMipsI16x8ExtractLane:
+    case kMipsI16x8ExtractLaneU:
+    case kMipsI16x8ExtractLaneS:
     case kMipsI16x8GeS:
     case kMipsI16x8GeU:
     case kMipsI16x8GtS:
@@ -163,7 +164,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsI8x16AddSaturateS:
     case kMipsI8x16AddSaturateU:
     case kMipsI8x16Eq:
-    case kMipsI8x16ExtractLane:
+    case kMipsI8x16ExtractLaneU:
+    case kMipsI8x16ExtractLaneS:
     case kMipsI8x16GeS:
     case kMipsI8x16GeU:
     case kMipsI8x16GtS:

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -2168,12 +2168,17 @@ SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
 SIMD_VISIT_SPLAT(F64x2)
 #undef SIMD_VISIT_SPLAT
 
-#define SIMD_VISIT_EXTRACT_LANE(Type)                              \
-  void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
-    VisitRRI(this, kMips##Type##ExtractLane, node);                \
-  }
-SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
-SIMD_VISIT_EXTRACT_LANE(F64x2)
+#define SIMD_VISIT_EXTRACT_LANE(Type, Sign)                              \
+  void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
+    VisitRRI(this, kMips##Type##ExtractLane##Sign, node);                \
+  }
+SIMD_VISIT_EXTRACT_LANE(F64x2, )
+SIMD_VISIT_EXTRACT_LANE(F32x4, )
+SIMD_VISIT_EXTRACT_LANE(I32x4, )
+SIMD_VISIT_EXTRACT_LANE(I16x8, U)
+SIMD_VISIT_EXTRACT_LANE(I16x8, S)
+SIMD_VISIT_EXTRACT_LANE(I8x16, U)
+SIMD_VISIT_EXTRACT_LANE(I8x16, S)
 #undef SIMD_VISIT_EXTRACT_LANE
 
 #define SIMD_VISIT_REPLACE_LANE(Type)                              \

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -2415,7 +2415,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
       break;
     }
-    case kMips64I16x8ExtractLane: {
+    case kMips64I16x8ExtractLaneU: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ copy_u_h(i.OutputRegister(), i.InputSimd128Register(0),
+                  i.InputInt8(1));
+      break;
+    }
+    case kMips64I16x8ExtractLaneS: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ copy_s_h(i.OutputRegister(), i.InputSimd128Register(0),
                   i.InputInt8(1));
@@ -2564,7 +2570,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ fill_b(i.OutputSimd128Register(), i.InputRegister(0));
       break;
     }
-    case kMips64I8x16ExtractLane: {
+    case kMips64I8x16ExtractLaneU: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ copy_u_b(i.OutputRegister(), i.InputSimd128Register(0),
+                  i.InputInt8(1));
+      break;
+    }
+    case kMips64I8x16ExtractLaneS: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ copy_s_b(i.OutputRegister(), i.InputSimd128Register(0),
                   i.InputInt8(1));

src/compiler/backend/mips64/instruction-codes-mips64.h

@@ -231,7 +231,8 @@ namespace compiler {
   V(Mips64I32x4GtU)                          \
   V(Mips64I32x4GeU)                          \
   V(Mips64I16x8Splat)                        \
-  V(Mips64I16x8ExtractLane)                  \
+  V(Mips64I16x8ExtractLaneU)                 \
+  V(Mips64I16x8ExtractLaneS)                 \
   V(Mips64I16x8ReplaceLane)                  \
   V(Mips64I16x8Neg)                          \
   V(Mips64I16x8Shl)                          \
@@ -256,7 +257,8 @@ namespace compiler {
   V(Mips64I16x8GtU)                          \
   V(Mips64I16x8GeU)                          \
   V(Mips64I8x16Splat)                        \
-  V(Mips64I8x16ExtractLane)                  \
+  V(Mips64I8x16ExtractLaneU)                 \
+  V(Mips64I8x16ExtractLaneS)                 \
   V(Mips64I8x16ReplaceLane)                  \
   V(Mips64I8x16Neg)                          \
   V(Mips64I8x16Shl)                          \

src/compiler/backend/mips64/instruction-scheduler-mips64.cc

@@ -134,7 +134,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64I16x8AddSaturateS:
     case kMips64I16x8AddSaturateU:
     case kMips64I16x8Eq:
-    case kMips64I16x8ExtractLane:
+    case kMips64I16x8ExtractLaneU:
+    case kMips64I16x8ExtractLaneS:
     case kMips64I16x8GeS:
     case kMips64I16x8GeU:
     case kMips64I16x8GtS:
@@ -193,7 +194,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64I8x16AddSaturateS:
     case kMips64I8x16AddSaturateU:
     case kMips64I8x16Eq:
-    case kMips64I8x16ExtractLane:
+    case kMips64I8x16ExtractLaneU:
+    case kMips64I8x16ExtractLaneS:
     case kMips64I8x16GeS:
     case kMips64I8x16GeU:
     case kMips64I8x16GtS:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -2839,12 +2839,17 @@ SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
 SIMD_VISIT_SPLAT(F64x2)
 #undef SIMD_VISIT_SPLAT
 
-#define SIMD_VISIT_EXTRACT_LANE(Type)                              \
-  void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
-    VisitRRI(this, kMips64##Type##ExtractLane, node);              \
-  }
-SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
-SIMD_VISIT_EXTRACT_LANE(F64x2)
+#define SIMD_VISIT_EXTRACT_LANE(Type, Sign)                              \
+  void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
+    VisitRRI(this, kMips64##Type##ExtractLane##Sign, node);              \
+  }
+SIMD_VISIT_EXTRACT_LANE(F64x2, )
+SIMD_VISIT_EXTRACT_LANE(F32x4, )
+SIMD_VISIT_EXTRACT_LANE(I32x4, )
+SIMD_VISIT_EXTRACT_LANE(I16x8, U)
+SIMD_VISIT_EXTRACT_LANE(I16x8, S)
+SIMD_VISIT_EXTRACT_LANE(I8x16, U)
+SIMD_VISIT_EXTRACT_LANE(I8x16, S)
 #undef SIMD_VISIT_EXTRACT_LANE
 
 #define SIMD_VISIT_REPLACE_LANE(Type)                              \