[wasm-simd][x64] Merge i8x16 and i16x8 extract lane with pextr

i8x16.extract_lane_u is pextrb, and i16x8.extract_lane_u is pextrw, we
can merge them instead of having separate opcodes.

R=bbudge@chromium.org

Bug: v8:10975
Change-Id: I7793a795905157b6094b1470d3437988c982af91
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2481834Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70771}

src/compiler/backend/x64/code-generator-x64.cc

@@ -3042,11 +3042,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Pshufd(dst, dst, uint8_t{0x0});
       break;
     }
-    case kX64I16x8ExtractLaneU: {
-      Register dst = i.OutputRegister();
-      __ Pextrw(dst, i.InputSimd128Register(0), i.InputUint8(1));
-      break;
-    }
     case kX64I16x8ExtractLaneS: {
       Register dst = i.OutputRegister();
       __ Pextrw(dst, i.InputSimd128Register(0), i.InputUint8(1));
@@ -3224,31 +3219,30 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Pshufb(dst, kScratchDoubleReg);
       break;
     }
-    case kX64I8x16ExtractLaneU: {
-      Register dst = i.OutputRegister();
-      __ Pextrb(dst, i.InputSimd128Register(0), i.InputUint8(1));
-      break;
-    }
     case kX64Pextrb: {
       EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset());
-      DCHECK(HasAddressingMode(instr));
-      DCHECK(!instr->HasOutput());
-
       size_t index = 0;
-      Operand operand = i.MemoryOperand(&index);
-      __ Pextrb(operand, i.InputSimd128Register(index),
-                i.InputUint8(index + 1));
+      if (HasAddressingMode(instr)) {
+        Operand operand = i.MemoryOperand(&index);
+        __ Pextrb(operand, i.InputSimd128Register(index),
+                  i.InputUint8(index + 1));
+      } else {
+        __ Pextrb(i.OutputRegister(), i.InputSimd128Register(0),
+                  i.InputUint8(1));
+      }
       break;
     }
     case kX64Pextrw: {
       EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset());
-      DCHECK(HasAddressingMode(instr));
-      DCHECK(!instr->HasOutput());
-
       size_t index = 0;
-      Operand operand = i.MemoryOperand(&index);
-      __ Pextrw(operand, i.InputSimd128Register(index),
-                i.InputUint8(index + 1));
+      if (HasAddressingMode(instr)) {
+        Operand operand = i.MemoryOperand(&index);
+        __ Pextrw(operand, i.InputSimd128Register(index),
+                  i.InputUint8(index + 1));
+      } else {
+        __ Pextrw(i.OutputRegister(), i.InputSimd128Register(0),
+                  i.InputUint8(1));
+      }
       break;
     }
     case kX64I8x16ExtractLaneS: {

src/compiler/backend/x64/instruction-codes-x64.h

@@ -241,7 +241,6 @@ namespace compiler {
   V(X64I32x4BitMask)                      \
   V(X64I32x4DotI16x8S)                    \
   V(X64I16x8Splat)                        \
-  V(X64I16x8ExtractLaneU)                 \
   V(X64I16x8ExtractLaneS)                 \
   V(X64I16x8SConvertI8x16Low)             \
   V(X64I16x8SConvertI8x16High)            \
@@ -275,7 +274,6 @@ namespace compiler {
   V(X64I16x8Abs)                          \
   V(X64I16x8BitMask)                      \
   V(X64I8x16Splat)                        \
-  V(X64I8x16ExtractLaneU)                 \
   V(X64I8x16ExtractLaneS)                 \
   V(X64Pinsrb)                            \
   V(X64Pinsrw)                            \

src/compiler/backend/x64/instruction-scheduler-x64.cc

@@ -217,7 +217,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64I32x4BitMask:
     case kX64I32x4DotI16x8S:
     case kX64I16x8Splat:
-    case kX64I16x8ExtractLaneU:
     case kX64I16x8ExtractLaneS:
     case kX64I16x8SConvertI8x16Low:
     case kX64I16x8SConvertI8x16High:
@@ -251,7 +250,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64I16x8Abs:
     case kX64I16x8BitMask:
     case kX64I8x16Splat:
-    case kX64I8x16ExtractLaneU:
     case kX64I8x16ExtractLaneS:
     case kX64I8x16SConvertI16x8:
     case kX64I8x16Neg:

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -2983,21 +2983,21 @@ void InstructionSelector::VisitF32x4Splat(Node* node) {
   Emit(kX64F32x4Splat, dst, g.UseRegister(node->InputAt(0)));
 }
 
-#define SIMD_VISIT_EXTRACT_LANE(Type, Sign)                              \
-  void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
-    X64OperandGenerator g(this);                                         \
-    int32_t lane = OpParameter<int32_t>(node->op());                     \
-    Emit(kX64##Type##ExtractLane##Sign, g.DefineAsRegister(node),        \
-         g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));         \
-  }
-SIMD_VISIT_EXTRACT_LANE(F64x2, )
-SIMD_VISIT_EXTRACT_LANE(F32x4, )
-SIMD_VISIT_EXTRACT_LANE(I64x2, )
-SIMD_VISIT_EXTRACT_LANE(I32x4, )
-SIMD_VISIT_EXTRACT_LANE(I16x8, U)
-SIMD_VISIT_EXTRACT_LANE(I16x8, S)
-SIMD_VISIT_EXTRACT_LANE(I8x16, U)
-SIMD_VISIT_EXTRACT_LANE(I8x16, S)
+#define SIMD_VISIT_EXTRACT_LANE(Type, Sign, Op)                               \
+  void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) {      \
+    X64OperandGenerator g(this);                                              \
+    int32_t lane = OpParameter<int32_t>(node->op());                          \
+    Emit(kX64##Op, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), \
+         g.UseImmediate(lane));                                               \
+  }
+SIMD_VISIT_EXTRACT_LANE(F64x2, , F64x2ExtractLane)
+SIMD_VISIT_EXTRACT_LANE(F32x4, , F32x4ExtractLane)
+SIMD_VISIT_EXTRACT_LANE(I64x2, , I64x2ExtractLane)
+SIMD_VISIT_EXTRACT_LANE(I32x4, , I32x4ExtractLane)
+SIMD_VISIT_EXTRACT_LANE(I16x8, S, I16x8ExtractLaneS)
+SIMD_VISIT_EXTRACT_LANE(I16x8, U, Pextrw)
+SIMD_VISIT_EXTRACT_LANE(I8x16, S, I8x16ExtractLaneS)
+SIMD_VISIT_EXTRACT_LANE(I8x16, U, Pextrb)
 #undef SIMD_VISIT_EXTRACT_LANE
 
 void InstructionSelector::VisitF32x4ReplaceLane(Node* node) {