[mips][wasm-simd] Implement i64x2.mul

Port 9ff2de44 https://crrev.com/c/1994382

Change-Id: I045fd862f6ae026fd0e5637a685589bee149ab74
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2008981
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65936}

src/compiler/backend/mips/code-generator-mips.cc

@@ -2063,6 +2063,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                 i.InputSimd128Register(1));
       break;
     }
+    case kMipsI64x2Mul: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ mulv_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputSimd128Register(1));
+      break;
+    }
     case kMipsI64x2Neg: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);

src/compiler/backend/mips/instruction-codes-mips.h

@@ -157,6 +157,7 @@ namespace compiler {
   V(MipsF64x2Le)                   \
   V(MipsI64x2Add)                  \
   V(MipsI64x2Sub)                  \
+  V(MipsI64x2Mul)                  \
   V(MipsI64x2Neg)                  \
   V(MipsI64x2Shl)                  \
   V(MipsI64x2ShrS)                 \

src/compiler/backend/mips/instruction-scheduler-mips.cc

@@ -59,6 +59,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsF64x2ReplaceLane:
     case kMipsI64x2Add:
     case kMipsI64x2Sub:
+    case kMipsI64x2Mul:
     case kMipsI64x2Neg:
     case kMipsI64x2Shl:
     case kMipsI64x2ShrS:

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -2089,6 +2089,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Le, kMipsF64x2Le)                             \
   V(I64x2Add, kMipsI64x2Add)                           \
   V(I64x2Sub, kMipsI64x2Sub)                           \
+  V(I64x2Mul, kMipsI64x2Mul)                           \
   V(F32x4Add, kMipsF32x4Add)                           \
   V(F32x4AddHoriz, kMipsF32x4AddHoriz)                 \
   V(F32x4Sub, kMipsF32x4Sub)                           \

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -2149,6 +2149,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                 i.InputSimd128Register(1));
       break;
     }
+    case kMips64I64x2Mul: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ mulv_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputSimd128Register(1));
+      break;
+    }
     case kMips64I64x2Neg: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);

src/compiler/backend/mips64/instruction-codes-mips64.h

@@ -205,6 +205,7 @@ namespace compiler {
   V(Mips64F64x2ReplaceLane)                  \
   V(Mips64I64x2Add)                          \
   V(Mips64I64x2Sub)                          \
+  V(Mips64I64x2Mul)                          \
   V(Mips64I64x2Neg)                          \
   V(Mips64I64x2Shl)                          \
   V(Mips64I64x2ShrS)                         \

src/compiler/backend/mips64/instruction-scheduler-mips64.cc

@@ -84,6 +84,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64F64x2Le:
     case kMips64I64x2Add:
     case kMips64I64x2Sub:
+    case kMips64I64x2Mul:
     case kMips64I64x2Neg:
     case kMips64I64x2Shl:
     case kMips64I64x2ShrS:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -2756,6 +2756,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Le, kMips64F64x2Le)                             \
   V(I64x2Add, kMips64I64x2Add)                           \
   V(I64x2Sub, kMips64I64x2Sub)                           \
+  V(I64x2Mul, kMips64I64x2Mul)                           \
   V(F32x4Add, kMips64F32x4Add)                           \
   V(F32x4AddHoriz, kMips64F32x4AddHoriz)                 \
   V(F32x4Sub, kMips64F32x4Sub)                           \