Commit 14785e51 authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot

PPC/s390: Add bit left-rotation machine operator

Port c0eee179

Original Commit Message:

    ROL will be optional operator as arm, arm64 only have ROR.

    The reason for this CL is inefficient Wasm codegen for 64-bit
    left-rotation.

R=duongn@microsoft.com, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=
LOG=N

Change-Id: I2803237712e45235ac53be07a28b4dc0c0f4a329
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2173574Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#67521}
parent 3c400825
......@@ -889,6 +889,10 @@ void InstructionSelector::VisitWord64Sar(Node* node) {
}
#endif
void InstructionSelector::VisitWord32Rol(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitWord64Rol(Node* node) { UNREACHABLE(); }
// TODO(mbrandy): Absorb logical-and into rlwinm?
void InstructionSelector::VisitWord32Ror(Node* node) {
VisitRRO(this, kPPC_RotRight32, node, kShift32Imm);
......
......@@ -1156,6 +1156,10 @@ void InstructionSelector::VisitWord32PairSar(Node* node) {
}
#endif
void InstructionSelector::VisitWord32Rol(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitWord64Rol(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitWord32Ctz(Node* node) { UNREACHABLE(); }
#if V8_TARGET_ARCH_S390X
......
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