S390: Fix Mod64/ModU64 sequence

The CodeGenerator sequence for Mod64/ModU64 is incorrectly using
32-bit operations.  Fix Mod64/ModU64 to use 64-bit divides to calculate
the remainder.

Fix disassembly for DLR, which was reading the wrong bits for the two
register operands.

R=jyan@ca.ibm.com,michael_dawson@ca.ibm.com,mbrandy@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1839813006

Cr-Commit-Position: refs/heads/master@{#35121}

src/compiler/s390/code-generator-s390.cc

@@ -1165,10 +1165,15 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       break;
 #if V8_TARGET_ARCH_S390X
     case kS390_Mod64:
-      ASSEMBLE_MODULO(dr, srda);
+      __ LoadRR(r1, i.InputRegister(0));
+      __ dsgr(r0, i.InputRegister(1));  // R1: Dividend
+      __ ltgr(i.OutputRegister(), r0);  // Copy R0: Remainder to output
       break;
     case kS390_ModU64:
-      ASSEMBLE_MODULO(dlr, srdl);
+      __ LoadRR(r1, i.InputRegister(0));
+      __ LoadImmP(r0, Operand::Zero());
+      __ dlgr(r0, i.InputRegister(1));  // R0:R1: Dividend
+      __ ltgr(i.OutputRegister(), r0);  // Copy R0: Remainder to output
       break;
 #endif
     case kS390_AbsFloat:

src/s390/disasm-s390.cc

@@ -788,7 +788,7 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
       Format(instr, "slbr\t'r5,'r6");
       break;
     case DLR:
-      Format(instr, "dlr\t'r1,'r2");
+      Format(instr, "dlr\t'r5,'r6");
       break;
     case DLGR:
       Format(instr, "dlgr\t'r5,'r6");