[mips][wasm-simd] Implement i64x2.ne and i64x2 all_true

Port: 257c303f

Bug: v8:11347,v8:11348,chromium:1174498

Change-Id: I1198ff37045e895082014918ec8d9f339893c1a4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2706307
Auto-Submit: Liu yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#72853}

src/compiler/backend/mips/code-generator-mips.cc

@@ -2285,6 +2285,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                i.InputSimd128Register(1));
       break;
     }
+    case kMipsI64x2Ne: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ ceq_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      __ nor_v(i.OutputSimd128Register(), i.OutputSimd128Register(),
+               i.OutputSimd128Register());
+      break;
+    }
     case kMipsI64x2SConvertI32x4Low: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       Simd128Register dst = i.OutputSimd128Register();
@@ -3111,6 +3119,17 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ bind(&all_false);
       break;
     }
+    case kMipsV64x2AllTrue: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ BranchMSA(&all_true, MSA_BRANCH_D, all_not_zero,
+                   i.InputSimd128Register(0), USE_DELAY_SLOT);
+      __ li(dst, -1);  // branch delay slot
+      __ li(dst, 0);
+      __ bind(&all_true);
+      break;
+    }
     case kMipsV32x4AllTrue: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       Register dst = i.OutputRegister();

src/compiler/backend/mips/instruction-codes-mips.h

@@ -172,6 +172,7 @@ namespace compiler {
   V(MipsI64x2ShrU)                 \
   V(MipsI64x2BitMask)              \
   V(MipsI64x2Eq)                   \
+  V(MipsI64x2Ne)                   \
   V(MipsI64x2SConvertI32x4Low)     \
   V(MipsI64x2SConvertI32x4High)    \
   V(MipsI64x2UConvertI32x4Low)     \
@@ -306,6 +307,7 @@ namespace compiler {
   V(MipsS128Not)                   \
   V(MipsS128Select)                \
   V(MipsS128AndNot)                \
+  V(MipsV64x2AllTrue)              \
   V(MipsV32x4AllTrue)              \
   V(MipsV16x8AllTrue)              \
   V(MipsV8x16AllTrue)              \

src/compiler/backend/mips/instruction-scheduler-mips.cc

@@ -75,6 +75,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsI64x2ShrU:
     case kMipsI64x2BitMask:
     case kMipsI64x2Eq:
+    case kMipsI64x2Ne:
     case kMipsI64x2SConvertI32x4Low:
     case kMipsI64x2SConvertI32x4High:
     case kMipsI64x2UConvertI32x4Low:
@@ -280,6 +281,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsS16x8InterleaveRight:
     case kMipsS16x8PackEven:
     case kMipsS16x8PackOdd:
+    case kMipsV64x2AllTrue:
     case kMipsV32x4AllTrue:
     case kMipsV16x8AllTrue:
     case kMipsV8x16AllTrue:

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -2160,6 +2160,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16Popcnt, kMipsI8x16Popcnt)                         \
   V(I8x16BitMask, kMipsI8x16BitMask)                       \
   V(S128Not, kMipsS128Not)                                 \
+  V(V64x2AllTrue, kMipsV64x2AllTrue)                       \
   V(V32x4AllTrue, kMipsV32x4AllTrue)                       \
   V(V16x8AllTrue, kMipsV16x8AllTrue)                       \
   V(V8x16AllTrue, kMipsV8x16AllTrue)                       \
@@ -2191,6 +2192,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Lt, kMipsF64x2Lt)                               \
   V(F64x2Le, kMipsF64x2Le)                               \
   V(I64x2Eq, kMipsI64x2Eq)                               \
+  V(I64x2Ne, kMipsI64x2Ne)                               \
   V(I64x2Add, kMipsI64x2Add)                             \
   V(I64x2Sub, kMipsI64x2Sub)                             \
   V(I64x2Mul, kMipsI64x2Mul)                             \

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -2427,6 +2427,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                i.InputSimd128Register(1));
       break;
     }
+    case kMips64I64x2Ne: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ ceq_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      __ nor_v(i.OutputSimd128Register(), i.OutputSimd128Register(),
+               i.OutputSimd128Register());
+      break;
+    }
     case kMips64I64x2SConvertI32x4Low: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       Simd128Register dst = i.OutputSimd128Register();
@@ -3310,6 +3318,17 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ bind(&all_false);
       break;
     }
+    case kMips64V64x2AllTrue: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      Register dst = i.OutputRegister();
+      Label all_true;
+      __ BranchMSA(&all_true, MSA_BRANCH_D, all_not_zero,
+                   i.InputSimd128Register(0), USE_DELAY_SLOT);
+      __ li(dst, 1);  // branch delay slot
+      __ li(dst, 0l);
+      __ bind(&all_true);
+      break;
+    }
     case kMips64V32x4AllTrue: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       Register dst = i.OutputRegister();

src/compiler/backend/mips64/instruction-codes-mips64.h

@@ -225,6 +225,7 @@ namespace compiler {
   V(Mips64I64x2ShrU)                         \
   V(Mips64I64x2BitMask)                      \
   V(Mips64I64x2Eq)                           \
+  V(Mips64I64x2Ne)                           \
   V(Mips64I64x2SConvertI32x4Low)             \
   V(Mips64I64x2SConvertI32x4High)            \
   V(Mips64I64x2UConvertI32x4Low)             \
@@ -331,6 +332,7 @@ namespace compiler {
   V(Mips64S128Not)                           \
   V(Mips64S128Select)                        \
   V(Mips64S128AndNot)                        \
+  V(Mips64V64x2AllTrue)                      \
   V(Mips64V32x4AllTrue)                      \
   V(Mips64V16x8AllTrue)                      \
   V(Mips64V8x16AllTrue)                      \

src/compiler/backend/mips64/instruction-scheduler-mips64.cc

@@ -103,6 +103,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64I64x2ShrU:
     case kMips64I64x2BitMask:
     case kMips64I64x2Eq:
+    case kMips64I64x2Ne:
     case kMips64I64x2SConvertI32x4Low:
     case kMips64I64x2SConvertI32x4High:
     case kMips64I64x2UConvertI32x4Low:
@@ -299,6 +300,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64S16x8PackOdd:
     case kMips64S16x2Reverse:
     case kMips64S16x4Reverse:
+    case kMips64V64x2AllTrue:
     case kMips64V32x4AllTrue:
     case kMips64V16x8AllTrue:
     case kMips64V8x16AllTrue:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -2898,6 +2898,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16Popcnt, kMips64I8x16Popcnt)                         \
   V(I8x16BitMask, kMips64I8x16BitMask)                       \
   V(S128Not, kMips64S128Not)                                 \
+  V(V64x2AllTrue, kMips64V64x2AllTrue)                       \
   V(V32x4AllTrue, kMips64V32x4AllTrue)                       \
   V(V16x8AllTrue, kMips64V16x8AllTrue)                       \
   V(V8x16AllTrue, kMips64V8x16AllTrue)                       \
@@ -2929,6 +2930,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Lt, kMips64F64x2Lt)                             \
   V(F64x2Le, kMips64F64x2Le)                             \
   V(I64x2Eq, kMips64I64x2Eq)                             \
+  V(I64x2Ne, kMips64I64x2Ne)                             \
   V(I64x2Add, kMips64I64x2Add)                           \
   V(I64x2Sub, kMips64I64x2Sub)                           \
   V(I64x2Mul, kMips64I64x2Mul)                           \