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Commit 12b7c452 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: Implement simd f32x2 unops 

Implementations are added to macro-assembler to be shared between
liftoff and code generator.

Change-Id: I945e312b45d87e021ffd64948bdfd69d0642fb83
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3387608Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78630}
parent 2e147b4f
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Showing with 65 additions and 111 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ 12b7c452
......@@ -5228,14 +5228,21 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
}
#define SIMD_UNOP_LIST_VRR_A(V) \
V(F64x2Abs, vfpso, 2, 0, 3) \
V(F64x2Neg, vfpso, 0, 0, 3) \
V(F64x2Sqrt, vfsq, 0, 0, 3) \
V(F64x2Ceil, vfi, 6, 0, 3) \
V(F64x2Floor, vfi, 7, 0, 3) \
V(F64x2Trunc, vfi, 5, 0, 3) \
V(F64x2NearestInt, vfi, 4, 0, 3)
#define SIMD_UNOP_LIST_VRR_A(V) \
V(F64x2Abs, vfpso, 2, 0, 3) \
V(F64x2Neg, vfpso, 0, 0, 3) \
V(F64x2Sqrt, vfsq, 0, 0, 3) \
V(F64x2Ceil, vfi, 6, 0, 3) \
V(F64x2Floor, vfi, 7, 0, 3) \
V(F64x2Trunc, vfi, 5, 0, 3) \
V(F64x2NearestInt, vfi, 4, 0, 3) \
V(F32x4Abs, vfpso, 2, 0, 2) \
V(F32x4Neg, vfpso, 0, 0, 2) \
V(F32x4Sqrt, vfsq, 0, 0, 2) \
V(F32x4Ceil, vfi, 6, 0, 2) \
V(F32x4Floor, vfi, 7, 0, 2) \
V(F32x4Trunc, vfi, 5, 0, 2) \
V(F32x4NearestInt, vfi, 4, 0, 2)
#define EMIT_SIMD_UNOP_VRR_A(name, op, c1, c2, c3) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
......
src/codegen/s390/macro-assembler-s390.h
View file @ 12b7c452
......@@ -1113,7 +1113,14 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F64x2Ceil) \
V(F64x2Floor) \
V(F64x2Trunc) \
V(F64x2NearestInt)
V(F64x2NearestInt) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4Sqrt) \
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc) \
V(F32x4NearestInt)
#define PROTOTYPE_SIMD_UNOP(name) \
void name(Simd128Register dst, Simd128Register src);
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ 12b7c452
......@@ -2643,20 +2643,27 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Splat, Simd128Register, DoubleRegister) \
V(F32x4Splat, Simd128Register, DoubleRegister) \
V(I64x2Splat, Simd128Register, Register) \
V(I32x4Splat, Simd128Register, Register) \
V(I16x8Splat, Simd128Register, Register) \
V(I8x16Splat, Simd128Register, Register) \
V(F64x2Abs, Simd128Register, Simd128Register) \
V(F64x2Neg, Simd128Register, Simd128Register) \
V(F64x2Sqrt, Simd128Register, Simd128Register) \
V(F64x2Ceil, Simd128Register, Simd128Register) \
V(F64x2Floor, Simd128Register, Simd128Register) \
V(F64x2Trunc, Simd128Register, Simd128Register) \
V(F64x2NearestInt, Simd128Register, Simd128Register)
#define SIMD_UNOP_LIST(V) \
V(F64x2Splat, Simd128Register, DoubleRegister) \
V(F32x4Splat, Simd128Register, DoubleRegister) \
V(I64x2Splat, Simd128Register, Register) \
V(I32x4Splat, Simd128Register, Register) \
V(I16x8Splat, Simd128Register, Register) \
V(I8x16Splat, Simd128Register, Register) \
V(F64x2Abs, Simd128Register, Simd128Register) \
V(F64x2Neg, Simd128Register, Simd128Register) \
V(F64x2Sqrt, Simd128Register, Simd128Register) \
V(F64x2Ceil, Simd128Register, Simd128Register) \
V(F64x2Floor, Simd128Register, Simd128Register) \
V(F64x2Trunc, Simd128Register, Simd128Register) \
V(F64x2NearestInt, Simd128Register, Simd128Register) \
V(F32x4Abs, Simd128Register, Simd128Register) \
V(F32x4Neg, Simd128Register, Simd128Register) \
V(F32x4Sqrt, Simd128Register, Simd128Register) \
V(F32x4Ceil, Simd128Register, Simd128Register) \
V(F32x4Floor, Simd128Register, Simd128Register) \
V(F32x4Trunc, Simd128Register, Simd128Register) \
V(F32x4NearestInt, Simd128Register, Simd128Register)
#define EMIT_SIMD_UNOP(name, dtype, stype) \
case kS390_##name: { \
......@@ -2749,16 +2756,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
// vector unary ops
case kS390_F32x4Abs: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(2), Condition(0), Condition(2));
break;
}
case kS390_F32x4Neg: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_I64x2Neg: {
__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
Condition(0), Condition(3));
......@@ -2799,11 +2796,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(2));
break;
}
case kS390_F32x4Sqrt: {
__ vfsq(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_S128Not: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
......@@ -3266,26 +3258,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(3));
break;
}
case kS390_F32x4Ceil: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(6),
Condition(0), Condition(2));
break;
}
case kS390_F32x4Floor: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(7),
Condition(0), Condition(2));
break;
}
case kS390_F32x4Trunc: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(5),
Condition(0), Condition(2));
break;
}
case kS390_F32x4NearestInt: {
__ vfi(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(4),
Condition(0), Condition(2));
break;
}
case kS390_I32x4DotI16x8S: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vme(kScratchDoubleReg, i.InputSimd128Register(0),
......
src/wasm/baseline/s390/liftoff-assembler-s390.h
View file @ 12b7c452
......@@ -2376,20 +2376,27 @@ SIMD_BINOP_RI_LIST(EMIT_SIMD_BINOP_RI)
#undef EMIT_SIMD_BINOP_RI
#undef SIMD_BINOP_RI_LIST
#define SIMD_UNOP_LIST(V) \
V(f64x2_splat, F64x2Splat, fp, fp, , void) \
V(f32x4_splat, F32x4Splat, fp, fp, , void) \
V(i64x2_splat, I64x2Splat, fp, gp, , void) \
V(i32x4_splat, I32x4Splat, fp, gp, , void) \
V(i16x8_splat, I16x8Splat, fp, gp, , void) \
V(i8x16_splat, I8x16Splat, fp, gp, , void) \
V(f64x2_abs, F64x2Abs, fp, fp, , void) \
V(f64x2_neg, F64x2Neg, fp, fp, , void) \
V(f64x2_sqrt, F64x2Sqrt, fp, fp, , void) \
V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool)
#define SIMD_UNOP_LIST(V) \
V(f64x2_splat, F64x2Splat, fp, fp, , void) \
V(f32x4_splat, F32x4Splat, fp, fp, , void) \
V(i64x2_splat, I64x2Splat, fp, gp, , void) \
V(i32x4_splat, I32x4Splat, fp, gp, , void) \
V(i16x8_splat, I16x8Splat, fp, gp, , void) \
V(i8x16_splat, I8x16Splat, fp, gp, , void) \
V(f64x2_abs, F64x2Abs, fp, fp, , void) \
V(f64x2_neg, F64x2Neg, fp, fp, , void) \
V(f64x2_sqrt, F64x2Sqrt, fp, fp, , void) \
V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool) \
V(f32x4_abs, F32x4Abs, fp, fp, , void) \
V(f32x4_neg, F32x4Neg, fp, fp, , void) \
V(f32x4_sqrt, F32x4Sqrt, fp, fp, , void) \
V(f32x4_ceil, F32x4Ceil, fp, fp, true, bool) \
V(f32x4_floor, F32x4Floor, fp, fp, true, bool) \
V(f32x4_trunc, F32x4Trunc, fp, fp, true, bool) \
V(f32x4_nearest_int, F32x4NearestInt, fp, fp, true, bool)
#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
......@@ -2491,45 +2498,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
bailout(kSimd, "f64x2.promote_low_f32x4");
}
void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4_abs");
}
void LiftoffAssembler::emit_f32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4neg");
}
void LiftoffAssembler::emit_f32x4_sqrt(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4sqrt");
}
bool LiftoffAssembler::emit_f32x4_ceil(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.ceil");
return true;
}
bool LiftoffAssembler::emit_f32x4_floor(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.floor");
return true;
}
bool LiftoffAssembler::emit_f32x4_trunc(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.trunc");
return true;
}
bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f32x4.nearest_int");
return true;
}
void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmin unimplemented");
......
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