PPC: [wasm-simd] Implement simd ExtractLane

Change-Id: Ic71dda9c487b6afa95ba2525518c923f2608fd7d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2187003Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#67661}

src/codegen/ppc/assembler-ppc.cc

@@ -1758,6 +1758,16 @@ void Assembler::fmsub(const DoubleRegister frt, const DoubleRegister fra,
 }
 
 // Vector instructions
+void Assembler::mfvsrd(const Register ra, const DoubleRegister rs) {
+  int SX = 1;
+  emit(MFVSRD | rs.code() * B21 | ra.code() * B16 | SX);
+}
+
+void Assembler::mfvsrwz(const Register ra, const DoubleRegister rs) {
+  int SX = 1;
+  emit(MFVSRWZ | rs.code() * B21 | ra.code() * B16 | SX);
+}
+
 void Assembler::mtvsrd(const DoubleRegister rt, const Register ra) {
   int TX = 1;
   emit(MTVSRD | rt.code() * B21 | ra.code() * B16 | TX);

src/codegen/ppc/assembler-ppc.h

@@ -947,6 +947,8 @@ class Assembler : public AssemblerBase {
              RCBit rc = LeaveRC);
 
   // Vector instructions
+  void mfvsrd(const Register ra, const DoubleRegister r);
+  void mfvsrwz(const Register ra, const DoubleRegister r);
   void mtvsrd(const DoubleRegister rt, const Register ra);
   void vor(const DoubleRegister rt, const DoubleRegister ra,
            const DoubleRegister rb);

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -2208,6 +2208,46 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vspltb(dst, dst, Operand(7));
       break;
     }
+    case kPPC_F64x2ExtractLane: {
+      __ mfvsrd(kScratchReg, i.InputSimd128Register(0));
+      __ MovInt64ToDouble(i.OutputDoubleRegister(), kScratchReg);
+      break;
+    }
+    case kPPC_F32x4ExtractLane: {
+      __ mfvsrwz(kScratchReg, i.InputSimd128Register(0));
+      __ MovIntToFloat(i.OutputDoubleRegister(), kScratchReg);
+      break;
+    }
+    case kPPC_I64x2ExtractLane: {
+      __ mfvsrd(i.OutputRegister(), i.InputSimd128Register(0));
+      break;
+    }
+    case kPPC_I32x4ExtractLane: {
+      __ mfvsrwz(i.OutputRegister(), i.InputSimd128Register(0));
+      break;
+    }
+    case kPPC_I16x8ExtractLaneU: {
+      __ mfvsrwz(r0, i.InputSimd128Register(0));
+      __ li(ip, Operand(16));
+      __ srd(i.OutputRegister(), r0, ip);
+      break;
+    }
+    case kPPC_I16x8ExtractLaneS: {
+      __ mfvsrwz(kScratchReg, i.InputSimd128Register(0));
+      __ sradi(i.OutputRegister(), kScratchReg, 16);
+      break;
+    }
+    case kPPC_I8x16ExtractLaneU: {
+      __ mfvsrwz(r0, i.InputSimd128Register(0));
+      __ li(ip, Operand(24));
+      __ srd(i.OutputRegister(), r0, ip);
+      break;
+    }
+    case kPPC_I8x16ExtractLaneS: {
+      __ mfvsrwz(kScratchReg, i.InputSimd128Register(0));
+      __ sradi(i.OutputRegister(), kScratchReg, 24);
+      break;
+    }
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -191,11 +191,19 @@ namespace compiler {
   V(PPC_AtomicXorInt32)              \
   V(PPC_AtomicXorInt64)              \
   V(PPC_F64x2Splat)                  \
+  V(PPC_F64x2ExtractLane)            \
   V(PPC_F32x4Splat)                  \
+  V(PPC_F32x4ExtractLane)            \
   V(PPC_I64x2Splat)                  \
+  V(PPC_I64x2ExtractLane)            \
   V(PPC_I32x4Splat)                  \
+  V(PPC_I32x4ExtractLane)            \
   V(PPC_I16x8Splat)                  \
+  V(PPC_I16x8ExtractLaneU)           \
+  V(PPC_I16x8ExtractLaneS)           \
   V(PPC_I8x16Splat)                  \
+  V(PPC_I8x16ExtractLaneU)           \
+  V(PPC_I8x16ExtractLaneS)           \
   V(PPC_StoreCompressTagged)         \
   V(PPC_LoadDecompressTaggedSigned)  \
   V(PPC_LoadDecompressTaggedPointer) \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -114,11 +114,19 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_CompressPointer:
     case kPPC_CompressAny:
     case kPPC_F64x2Splat:
+    case kPPC_F64x2ExtractLane:
     case kPPC_F32x4Splat:
+    case kPPC_F32x4ExtractLane:
     case kPPC_I64x2Splat:
+    case kPPC_I64x2ExtractLane:
     case kPPC_I32x4Splat:
+    case kPPC_I32x4ExtractLane:
     case kPPC_I16x8Splat:
+    case kPPC_I16x8ExtractLaneU:
+    case kPPC_I16x8ExtractLaneS:
     case kPPC_I8x16Splat:
+    case kPPC_I8x16ExtractLaneU:
+    case kPPC_I8x16ExtractLaneS:
       return kNoOpcodeFlags;
 
     case kPPC_LoadWordS8:

src/compiler/backend/ppc/instruction-selector-ppc.cc

@@ -2139,7 +2139,10 @@ SIMD_TYPES(SIMD_VISIT_SPLAT)
 
 #define SIMD_VISIT_EXTRACT_LANE(Type, Sign)                              \
   void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
-    UNIMPLEMENTED();                                                     \
+    PPCOperandGenerator g(this);                                         \
+    int32_t lane = OpParameter<int32_t>(node->op());                     \
+    Emit(kPPC_##Type##ExtractLane##Sign, g.DefineAsRegister(node),       \
+         g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));         \
   }
 SIMD_VISIT_EXTRACT_LANE(F64x2, )
 SIMD_VISIT_EXTRACT_LANE(F32x4, )