[wasm-simd][arm64] Add load and zero extend instructions

Load and zero extend is still in prototype phase [0], implementing for ARM64 in
order to get more benchmark results.

[0] https://github.com/WebAssembly/simd/pull/237

Bug: v8:10713
Change-Id: I7d632324e4bdb0934ab024911201a06b19a1a83d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2416407
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70069}

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -2647,6 +2647,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Uxtl(i.OutputSimd128Register().V2D(), i.OutputSimd128Register().V2S());
       break;
     }
+    case kArm64S128LoadMem32Zero: {
+      __ Ldr(i.OutputSimd128Register().S(), i.MemoryOperand(0));
+      break;
+    }
+    case kArm64S128LoadMem64Zero: {
+      __ Ldr(i.OutputSimd128Register().D(), i.MemoryOperand(0));
+      break;
+    }
 #define SIMD_REDUCE_OP_CASE(Op, Instr, format, FORMAT)     \
   case Op: {                                               \
     UseScratchRegisterScope scope(tasm());                 \

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -425,7 +425,11 @@ namespace compiler {
   V(Arm64Word64AtomicCompareExchangeUint8)  \
   V(Arm64Word64AtomicCompareExchangeUint16) \
   V(Arm64Word64AtomicCompareExchangeUint32) \
-  V(Arm64Word64AtomicCompareExchangeUint64)
+  V(Arm64Word64AtomicCompareExchangeUint64) \
+  V(Arm64S128LoadMem32Zero)                 \
+  V(Arm64S128LoadMem64Zero)
+// TODO(v8:10930) Adding new codes before these atomic instructions causes a
+// mksnapshot error.
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -380,6 +380,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64I32x4Load16x4U:
     case kArm64I64x2Load32x2S:
     case kArm64I64x2Load32x2U:
+    case kArm64S128LoadMem32Zero:
+    case kArm64S128LoadMem64Zero:
       return kIsLoadOperation;
 
     case kArm64Claim:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -640,6 +640,12 @@ void InstructionSelector::VisitLoadTransform(Node* node) {
     case LoadTransformation::kI64x2Load32x2U:
       opcode = kArm64I64x2Load32x2U;
       break;
+    case LoadTransformation::kS128LoadMem32Zero:
+      opcode = kArm64S128LoadMem32Zero;
+      break;
+    case LoadTransformation::kS128LoadMem64Zero:
+      opcode = kArm64S128LoadMem64Zero;
+      break;
     default:
       UNIMPLEMENTED();
   }

test/cctest/wasm/test-run-wasm-simd.cc

@@ -3594,7 +3594,7 @@ WASM_SIMD_TEST(I64x2Load32x2S) {
 }
 
 // TODO(v8:10713): Prototyping v128.load32_zero and v128.load64_zero.
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 template <typename S>
 void RunLoadZeroTest(TestExecutionTier execution_tier, LowerSimd lower_simd,
                      WasmOpcode op) {
@@ -3626,7 +3626,7 @@ WASM_SIMD_TEST_NO_LOWERING(S128LoadMem32Zero) {
 WASM_SIMD_TEST_NO_LOWERING(S128LoadMem64Zero) {
   RunLoadZeroTest<int64_t>(execution_tier, lower_simd, kExprS128LoadMem64Zero);
 }
-#endif  // V8_TARGET_ARCH_X64
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 #define WASM_SIMD_ANYTRUE_TEST(format, lanes, max, param_type)                \
   WASM_SIMD_TEST(S##format##AnyTrue) {                                        \