PPC: [wasm-simd] Implement FP Multiply-ADD and subtract

Change-Id: Ic0e82d752046349d9f21f0001b84b23d73065fd6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2353032Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#69364}

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -3302,6 +3302,46 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                i.InputSimd128Register(1));
       break;
     }
+    case kPPC_F64x2Qfma: {
+      Simd128Register src0 = i.InputSimd128Register(0);
+      Simd128Register src1 = i.InputSimd128Register(1);
+      Simd128Register src2 = i.InputSimd128Register(2);
+      Simd128Register dst = i.OutputSimd128Register();
+      __ vor(kScratchDoubleReg, src1, src1);
+      __ xvmaddmdp(kScratchDoubleReg, src2, src0);
+      __ vor(dst, kScratchDoubleReg, kScratchDoubleReg);
+      break;
+    }
+    case kPPC_F64x2Qfms: {
+      Simd128Register src0 = i.InputSimd128Register(0);
+      Simd128Register src1 = i.InputSimd128Register(1);
+      Simd128Register src2 = i.InputSimd128Register(2);
+      Simd128Register dst = i.OutputSimd128Register();
+      __ vor(kScratchDoubleReg, src1, src1);
+      __ xvnmsubmdp(kScratchDoubleReg, src2, src0);
+      __ vor(dst, kScratchDoubleReg, kScratchDoubleReg);
+      break;
+    }
+    case kPPC_F32x4Qfma: {
+      Simd128Register src0 = i.InputSimd128Register(0);
+      Simd128Register src1 = i.InputSimd128Register(1);
+      Simd128Register src2 = i.InputSimd128Register(2);
+      Simd128Register dst = i.OutputSimd128Register();
+      __ vor(kScratchDoubleReg, src1, src1);
+      __ xvmaddmsp(kScratchDoubleReg, src2, src0);
+      __ vor(dst, kScratchDoubleReg, kScratchDoubleReg);
+      break;
+    }
+    case kPPC_F32x4Qfms: {
+      Simd128Register src0 = i.InputSimd128Register(0);
+      Simd128Register src1 = i.InputSimd128Register(1);
+      Simd128Register src2 = i.InputSimd128Register(2);
+      Simd128Register dst = i.OutputSimd128Register();
+      __ vor(kScratchDoubleReg, src1, src1);
+      __ xvnmsubmsp(kScratchDoubleReg, src2, src0);
+      __ vor(dst, kScratchDoubleReg, kScratchDoubleReg);
+      break;
+    }
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -205,6 +205,8 @@ namespace compiler {
   V(PPC_F64x2Abs)                    \
   V(PPC_F64x2Neg)                    \
   V(PPC_F64x2Sqrt)                   \
+  V(PPC_F64x2Qfma)                   \
+  V(PPC_F64x2Qfms)                   \
   V(PPC_F32x4Splat)                  \
   V(PPC_F32x4ExtractLane)            \
   V(PPC_F32x4ReplaceLane)            \
@@ -271,6 +273,8 @@ namespace compiler {
   V(PPC_I32x4SConvertI16x8High)      \
   V(PPC_I32x4UConvertI16x8Low)       \
   V(PPC_I32x4UConvertI16x8High)      \
+  V(PPC_F32x4Qfma)                   \
+  V(PPC_F32x4Qfms)                   \
   V(PPC_I16x8Splat)                  \
   V(PPC_I16x8ExtractLaneU)           \
   V(PPC_I16x8ExtractLaneS)           \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -128,6 +128,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_F64x2Abs:
     case kPPC_F64x2Neg:
     case kPPC_F64x2Sqrt:
+    case kPPC_F64x2Qfma:
+    case kPPC_F64x2Qfms:
     case kPPC_F32x4Splat:
     case kPPC_F32x4ExtractLane:
     case kPPC_F32x4ReplaceLane:
@@ -146,6 +148,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_F32x4Sqrt:
     case kPPC_F32x4SConvertI32x4:
     case kPPC_F32x4UConvertI32x4:
+    case kPPC_F32x4Qfma:
+    case kPPC_F32x4Qfms:
     case kPPC_I64x2Splat:
     case kPPC_I64x2ExtractLane:
     case kPPC_I64x2ReplaceLane: