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Commit 0d6270ca authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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PPC: [wasm-simd] Implement simd min/max operations 

Change-Id: I346d237515c589c65e2c073eea55cdbfc301688e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2233179Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68214}
parent c159f097
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Showing with 158 additions and 58 deletions
src/codegen/ppc/constants-ppc.h
View file @ 0d6270ca
...@@ -1707,8 +1707,6 @@ using Instr = uint32_t; ...@@ -1707,8 +1707,6 @@ using Instr = uint32_t;
V(stvewx, STVEWX, 0x7C00018E) \ V(stvewx, STVEWX, 0x7C00018E) \
/* Store Vector Indexed Last */ \ /* Store Vector Indexed Last */ \
V(stvxl, STVXL, 0x7C0003CE) \ V(stvxl, STVXL, 0x7C0003CE) \
/* Vector Minimum Signed Doubleword */ \
V(vminsd, VMINSD, 0x100003C2) \
/* Floating Merge Even Word */ \ /* Floating Merge Even Word */ \
V(fmrgew, FMRGEW, 0xFC00078C) \ V(fmrgew, FMRGEW, 0xFC00078C) \
/* Floating Merge Odd Word */ \ /* Floating Merge Odd Word */ \
...@@ -2252,7 +2250,39 @@ using Instr = uint32_t; ...@@ -2252,7 +2250,39 @@ using Instr = uint32_t;
/* Vector Sum across Half Signed Word Saturate */ \ /* Vector Sum across Half Signed Word Saturate */ \
V(vsum2sws, VSUM2SWS, 0x10000688) \ V(vsum2sws, VSUM2SWS, 0x10000688) \
/* Vector Pack Unsigned Doubleword Unsigned Modulo */ \ /* Vector Pack Unsigned Doubleword Unsigned Modulo */ \
V(vpkudum, VPKUDUM, 0x1000044E) V(vpkudum, VPKUDUM, 0x1000044E) \
/* Vector Maximum Signed Byte */ \
V(vmaxsb, VMAXSB, 0x10000102) \
/* Vector Maximum Unsigned Byte */ \
V(vmaxub, VMAXUB, 0x10000002) \
/* Vector Maximum Signed Doubleword */ \
V(vmaxsd, VMAXSD, 0x100001C2) \
/* Vector Maximum Unsigned Doubleword */ \
V(vmaxud, VMAXUD, 0x100000C2) \
/* Vector Maximum Signed Halfword */ \
V(vmaxsh, VMAXSH, 0x10000142) \
/* Vector Maximum Unsigned Halfword */ \
V(vmaxuh, VMAXUH, 0x10000042) \
/* Vector Maximum Signed Word */ \
V(vmaxsw, VMAXSW, 0x10000182) \
/* Vector Maximum Unsigned Word */ \
V(vmaxuw, VMAXUW, 0x10000082) \
/* Vector Minimum Signed Byte */ \
V(vminsb, VMINSB, 0x10000302) \
/* Vector Minimum Unsigned Byte */ \
V(vminub, VMINUB, 0x10000202) \
/* Vector Minimum Signed Doubleword */ \
V(vminsd, VMINSD, 0x100003C2) \
/* Vector Minimum Unsigned Doubleword */ \
V(vminud, VMINUD, 0x100002C2) \
/* Vector Minimum Signed Halfword */ \
V(vminsh, VMINSH, 0x10000342) \
/* Vector Minimum Unsigned Halfword */ \
V(vminuh, VMINUH, 0x10000242) \
/* Vector Minimum Signed Word */ \
V(vminsw, VMINSW, 0x10000382) \
/* Vector Minimum Unsigned Word */ \
V(vminuw, VMINUW, 0x10000282)
#define PPC_VX_OPCODE_UNUSED_LIST(V) \ #define PPC_VX_OPCODE_UNUSED_LIST(V) \
/* Decimal Add Modulo */ \ /* Decimal Add Modulo */ \
...@@ -2327,38 +2357,8 @@ using Instr = uint32_t; ...@@ -2327,38 +2357,8 @@ using Instr = uint32_t;
V(vlogefp, VLOGEFP, 0x100001CA) \ V(vlogefp, VLOGEFP, 0x100001CA) \
/* Vector Maximum Single-Precision */ \ /* Vector Maximum Single-Precision */ \
V(vmaxfp, VMAXFP, 0x1000040A) \ V(vmaxfp, VMAXFP, 0x1000040A) \
/* Vector Maximum Signed Byte */ \
V(vmaxsb, VMAXSB, 0x10000102) \
/* Vector Maximum Signed Doubleword */ \
V(vmaxsd, VMAXSD, 0x100001C2) \
/* Vector Maximum Signed Halfword */ \
V(vmaxsh, VMAXSH, 0x10000142) \
/* Vector Maximum Signed Word */ \
V(vmaxsw, VMAXSW, 0x10000182) \
/* Vector Maximum Unsigned Byte */ \
V(vmaxub, VMAXUB, 0x10000002) \
/* Vector Maximum Unsigned Doubleword */ \
V(vmaxud, VMAXUD, 0x100000C2) \
/* Vector Maximum Unsigned Halfword */ \
V(vmaxuh, VMAXUH, 0x10000042) \
/* Vector Maximum Unsigned Word */ \
V(vmaxuw, VMAXUW, 0x10000082) \
/* Vector Minimum Single-Precision */ \ /* Vector Minimum Single-Precision */ \
V(vminfp, VMINFP, 0x1000044A) \ V(vminfp, VMINFP, 0x1000044A) \
/* Vector Minimum Signed Byte */ \
V(vminsb, VMINSB, 0x10000302) \
/* Vector Minimum Signed Halfword */ \
V(vminsh, VMINSH, 0x10000342) \
/* Vector Minimum Signed Word */ \
V(vminsw, VMINSW, 0x10000382) \
/* Vector Minimum Unsigned Byte */ \
V(vminub, VMINUB, 0x10000202) \
/* Vector Minimum Unsigned Doubleword */ \
V(vminud, VMINUD, 0x100002C2) \
/* Vector Minimum Unsigned Halfword */ \
V(vminuh, VMINUH, 0x10000242) \
/* Vector Minimum Unsigned Word */ \
V(vminuw, VMINUW, 0x10000282) \
/* Vector Merge High Byte */ \ /* Vector Merge High Byte */ \
V(vmrghb, VMRGHB, 0x1000000C) \ V(vmrghb, VMRGHB, 0x1000000C) \
/* Vector Merge High Halfword */ \ /* Vector Merge High Halfword */ \
......
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ 0d6270ca
...@@ -2530,6 +2530,86 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -2530,6 +2530,86 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.OutputSimd128Register()); i.OutputSimd128Register());
break; break;
} }
case kPPC_I64x2MinS: {
__ vminsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MinS: {
__ vminsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MinU: {
__ vminud(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MinU: {
__ vminuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8MinS: {
__ vminsh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8MinU: {
__ vminuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16MinS: {
__ vminsb(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16MinU: {
__ vminub(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MaxS: {
__ vmaxsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MaxS: {
__ vmaxsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MaxU: {
__ vmaxud(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MaxU: {
__ vmaxuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8MaxS: {
__ vmaxsh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I16x8MaxU: {
__ vmaxuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16MaxS: {
__ vmaxsb(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I8x16MaxU: {
__ vmaxub(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_StoreCompressTagged: { case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX); ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break; break;
......
src/compiler/backend/ppc/instruction-codes-ppc.h
View file @ 0d6270ca
...@@ -209,6 +209,10 @@ namespace compiler { ...@@ -209,6 +209,10 @@ namespace compiler {
V(PPC_I64x2Add) \ V(PPC_I64x2Add) \
V(PPC_I64x2Sub) \ V(PPC_I64x2Sub) \
V(PPC_I64x2Mul) \ V(PPC_I64x2Mul) \
V(PPC_I64x2MinS) \
V(PPC_I64x2MinU) \
V(PPC_I64x2MaxS) \
V(PPC_I64x2MaxU) \
V(PPC_I32x4Splat) \ V(PPC_I32x4Splat) \
V(PPC_I32x4ExtractLane) \ V(PPC_I32x4ExtractLane) \
V(PPC_I32x4ReplaceLane) \ V(PPC_I32x4ReplaceLane) \
...@@ -216,6 +220,10 @@ namespace compiler { ...@@ -216,6 +220,10 @@ namespace compiler {
V(PPC_I32x4AddHoriz) \ V(PPC_I32x4AddHoriz) \
V(PPC_I32x4Sub) \ V(PPC_I32x4Sub) \
V(PPC_I32x4Mul) \ V(PPC_I32x4Mul) \
V(PPC_I32x4MinS) \
V(PPC_I32x4MinU) \
V(PPC_I32x4MaxS) \
V(PPC_I32x4MaxU) \
V(PPC_I16x8Splat) \ V(PPC_I16x8Splat) \
V(PPC_I16x8ExtractLaneU) \ V(PPC_I16x8ExtractLaneU) \
V(PPC_I16x8ExtractLaneS) \ V(PPC_I16x8ExtractLaneS) \
...@@ -224,6 +232,10 @@ namespace compiler { ...@@ -224,6 +232,10 @@ namespace compiler {
V(PPC_I16x8AddHoriz) \ V(PPC_I16x8AddHoriz) \
V(PPC_I16x8Sub) \ V(PPC_I16x8Sub) \
V(PPC_I16x8Mul) \ V(PPC_I16x8Mul) \
V(PPC_I16x8MinS) \
V(PPC_I16x8MinU) \
V(PPC_I16x8MaxS) \
V(PPC_I16x8MaxU) \
V(PPC_I8x16Splat) \ V(PPC_I8x16Splat) \
V(PPC_I8x16ExtractLaneU) \ V(PPC_I8x16ExtractLaneU) \
V(PPC_I8x16ExtractLaneS) \ V(PPC_I8x16ExtractLaneS) \
...@@ -231,6 +243,10 @@ namespace compiler { ...@@ -231,6 +243,10 @@ namespace compiler {
V(PPC_I8x16Add) \ V(PPC_I8x16Add) \
V(PPC_I8x16Sub) \ V(PPC_I8x16Sub) \
V(PPC_I8x16Mul) \ V(PPC_I8x16Mul) \
V(PPC_I8x16MinS) \
V(PPC_I8x16MinU) \
V(PPC_I8x16MaxS) \
V(PPC_I8x16MaxU) \
V(PPC_StoreCompressTagged) \ V(PPC_StoreCompressTagged) \
V(PPC_LoadDecompressTaggedSigned) \ V(PPC_LoadDecompressTaggedSigned) \
V(PPC_LoadDecompressTaggedPointer) \ V(PPC_LoadDecompressTaggedPointer) \
......
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
View file @ 0d6270ca
...@@ -132,6 +132,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -132,6 +132,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I64x2Add: case kPPC_I64x2Add:
case kPPC_I64x2Sub: case kPPC_I64x2Sub:
case kPPC_I64x2Mul: case kPPC_I64x2Mul:
case kPPC_I64x2MinS:
case kPPC_I64x2MinU:
case kPPC_I64x2MaxS:
case kPPC_I64x2MaxU:
case kPPC_I32x4Splat: case kPPC_I32x4Splat:
case kPPC_I32x4ExtractLane: case kPPC_I32x4ExtractLane:
case kPPC_I32x4ReplaceLane: case kPPC_I32x4ReplaceLane:
...@@ -139,6 +143,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -139,6 +143,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I32x4AddHoriz: case kPPC_I32x4AddHoriz:
case kPPC_I32x4Sub: case kPPC_I32x4Sub:
case kPPC_I32x4Mul: case kPPC_I32x4Mul:
case kPPC_I32x4MinS:
case kPPC_I32x4MinU:
case kPPC_I32x4MaxS:
case kPPC_I32x4MaxU:
case kPPC_I16x8Splat: case kPPC_I16x8Splat:
case kPPC_I16x8ExtractLaneU: case kPPC_I16x8ExtractLaneU:
case kPPC_I16x8ExtractLaneS: case kPPC_I16x8ExtractLaneS:
...@@ -147,6 +155,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -147,6 +155,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I16x8AddHoriz: case kPPC_I16x8AddHoriz:
case kPPC_I16x8Sub: case kPPC_I16x8Sub:
case kPPC_I16x8Mul: case kPPC_I16x8Mul:
case kPPC_I16x8MinS:
case kPPC_I16x8MinU:
case kPPC_I16x8MaxS:
case kPPC_I16x8MaxU:
case kPPC_I8x16Splat: case kPPC_I8x16Splat:
case kPPC_I8x16ExtractLaneU: case kPPC_I8x16ExtractLaneU:
case kPPC_I8x16ExtractLaneS: case kPPC_I8x16ExtractLaneS:
...@@ -154,6 +166,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -154,6 +166,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I8x16Add: case kPPC_I8x16Add:
case kPPC_I8x16Sub: case kPPC_I8x16Sub:
case kPPC_I8x16Mul: case kPPC_I8x16Mul:
case kPPC_I8x16MinS:
case kPPC_I8x16MinU:
case kPPC_I8x16MaxS:
case kPPC_I8x16MaxU:
return kNoOpcodeFlags; return kNoOpcodeFlags;
case kPPC_LoadWordS8: case kPPC_LoadWordS8:
......
src/compiler/backend/ppc/instruction-selector-ppc.cc
View file @ 0d6270ca
...@@ -2142,13 +2142,25 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2142,13 +2142,25 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4AddHoriz) \ V(I32x4AddHoriz) \
V(I32x4Sub) \ V(I32x4Sub) \
V(I32x4Mul) \ V(I32x4Mul) \
V(I32x4MinS) \
V(I32x4MinU) \
V(I32x4MaxS) \
V(I32x4MaxU) \
V(I16x8Add) \ V(I16x8Add) \
V(I16x8AddHoriz) \ V(I16x8AddHoriz) \
V(I16x8Sub) \ V(I16x8Sub) \
V(I16x8Mul) \ V(I16x8Mul) \
V(I16x8MinS) \
V(I16x8MinU) \
V(I16x8MaxS) \
V(I16x8MaxU) \
V(I8x16Add) \ V(I8x16Add) \
V(I8x16Sub) \ V(I8x16Sub) \
V(I8x16Mul) V(I8x16Mul) \
V(I8x16MinS) \
V(I8x16MinU) \
V(I8x16MaxS) \
V(I8x16MaxU)
#define SIMD_VISIT_SPLAT(Type) \ #define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \ void InstructionSelector::Visit##Type##Splat(Node* node) { \
...@@ -2210,18 +2222,10 @@ void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); } ...@@ -2210,18 +2222,10 @@ void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4ShrS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Eq(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Ne(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4Ne(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4MaxU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
...@@ -2248,10 +2252,6 @@ void InstructionSelector::VisitI16x8SubSaturateS(Node* node) { ...@@ -2248,10 +2252,6 @@ void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI16x8MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Eq(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Ne(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8Ne(Node* node) { UNIMPLEMENTED(); }
...@@ -2264,10 +2264,6 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) { ...@@ -2264,10 +2264,6 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI16x8MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MaxU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); }
...@@ -2296,10 +2292,6 @@ void InstructionSelector::VisitI8x16SubSaturateS(Node* node) { ...@@ -2296,10 +2292,6 @@ void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI8x16MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); }
...@@ -2316,10 +2308,6 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) { ...@@ -2316,10 +2308,6 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI8x16MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16MaxU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16GtU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16GtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16GeU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI8x16GeU(Node* node) { UNIMPLEMENTED(); }
......
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