Commit 0d01d17b authored by sgjesse@chromium.org's avatar sgjesse@chromium.org

Fix ARM thumb/debug build

Landing http://codereview.chromium.org/548007

TBR=piman@chromium.org
Review URL: http://codereview.chromium.org/549033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3591 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent caf177c6
...@@ -61,28 +61,32 @@ void CPU::FlushICache(void* start, size_t size) { ...@@ -61,28 +61,32 @@ void CPU::FlushICache(void* start, size_t size) {
reinterpret_cast<uint32_t>(start) + size; reinterpret_cast<uint32_t>(start) + size;
register uint32_t flg asm("a3") = 0; register uint32_t flg asm("a3") = 0;
#ifdef __ARM_EABI__ #ifdef __ARM_EABI__
register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
#if defined (__arm__) && !defined(__thumb__) #if defined (__arm__) && !defined(__thumb__)
// __arm__ may be defined in thumb mode. // __arm__ may be defined in thumb mode.
register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
asm volatile( asm volatile(
"swi 0x0" "swi 0x0"
: "=r" (beg) : "=r" (beg)
: "0" (beg), "r" (end), "r" (flg), "r" (scno)); : "0" (beg), "r" (end), "r" (flg), "r" (scno));
#else #else
// r7 is reserved by the EABI in thumb mode.
asm volatile( asm volatile(
"@ Enter ARM Mode \n\t" "@ Enter ARM Mode \n\t"
"adr r3, 1f \n\t" "adr r3, 1f \n\t"
"bx r3 \n\t" "bx r3 \n\t"
".ALIGN 4 \n\t" ".ALIGN 4 \n\t"
".ARM \n" ".ARM \n"
"1: swi 0x0 \n\t" "1: push {r7} \n\t"
"mov r7, %4 \n\t"
"swi 0x0 \n\t"
"pop {r7} \n\t"
"@ Enter THUMB Mode\n\t" "@ Enter THUMB Mode\n\t"
"adr r3, 2f+1 \n\t" "adr r3, 2f+1 \n\t"
"bx r3 \n\t" "bx r3 \n\t"
".THUMB \n" ".THUMB \n"
"2: \n\t" "2: \n\t"
: "=r" (beg) : "=r" (beg)
: "0" (beg), "r" (end), "r" (flg), "r" (scno) : "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
: "r3"); : "r3");
#endif #endif
#else #else
......
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