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Commit 0c5c4795 authored by dusan.m.milosavljevic's avatar dusan.m.milosavljevic Committed by Commit bot
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MIPS: [turbofan] Improve test and equality compare with zero and constants. 

TEST=
BUG=

Review URL: https://codereview.chromium.org/1400833002

Cr-Commit-Position: refs/heads/master@{#31222}
parent 32f13dfb
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Showing with 72 additions and 55 deletions
src/compiler/mips/code-generator-mips.cc
View file @ 0c5c4795
......@@ -968,19 +968,10 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
if (instr->arch_opcode() == kMipsTst) {
cc = FlagsConditionToConditionTst(condition);
__ And(kScratchReg, i.InputRegister(0), i.InputOperand(1));
__ xori(result, zero_reg, 1); // Create 1 for true.
if (IsMipsArchVariant(kMips32r6)) {
if (cc == eq) {
__ seleqz(result, result, kScratchReg);
} else {
__ selnez(result, result, kScratchReg);
}
} else {
if (cc == eq) {
__ Movn(result, zero_reg, kScratchReg);
} else {
__ Movz(result, zero_reg, kScratchReg);
}
__ Sltu(result, zero_reg, kScratchReg);
if (cc == eq) {
// Sltu produces 0 for equality, invert the result.
__ xori(result, result, 1);
}
return;
} else if (instr->arch_opcode() == kMipsAddOvf ||
......@@ -999,20 +990,18 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
case ne: {
Register left = i.InputRegister(0);
Operand right = i.InputOperand(1);
__ Subu(kScratchReg, left, right);
__ xori(result, zero_reg, 1);
if (IsMipsArchVariant(kMips32r6)) {
if (cc == eq) {
__ seleqz(result, result, kScratchReg);
} else {
__ selnez(result, result, kScratchReg);
}
Register select;
if (instr->InputAt(1)->IsImmediate() && right.immediate() == 0) {
// Pass left operand if right is zero.
select = left;
} else {
if (cc == eq) {
__ Movn(result, zero_reg, kScratchReg);
} else {
__ Movz(result, zero_reg, kScratchReg);
}
__ Subu(kScratchReg, left, right);
select = kScratchReg;
}
__ Sltu(result, zero_reg, select);
if (cc == eq) {
// Sltu produces 0 for equality, invert the result.
__ xori(result, result, 1);
}
} break;
case lt:
......
src/compiler/mips/instruction-selector-mips.cc
View file @ 0c5c4795
......@@ -44,11 +44,10 @@ class MipsOperandGenerator final : public OperandGenerator {
return is_uint16(value);
case kMipsLdc1:
case kMipsSdc1:
case kCheckedLoadFloat32:
case kCheckedLoadFloat64:
case kCheckedStoreFloat32:
case kCheckedStoreFloat64:
return is_int16(value + kIntSize);
return std::numeric_limits<int16_t>::min() <= (value + kIntSize) &&
std::numeric_limits<int16_t>::max() >= (value + kIntSize);
default:
return is_int16(value);
}
......@@ -826,6 +825,16 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
// Match immediates on left or right side of comparison.
if (g.CanBeImmediate(right, opcode)) {
switch (cont->condition()) {
case kEqual:
case kNotEqual:
if (cont->IsSet()) {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseImmediate(right), cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseRegister(right), cont);
}
break;
case kSignedLessThan:
case kSignedGreaterThanOrEqual:
case kUnsignedLessThan:
......@@ -840,6 +849,16 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
} else if (g.CanBeImmediate(left, opcode)) {
if (!commutative) cont->Commute();
switch (cont->condition()) {
case kEqual:
case kNotEqual:
if (cont->IsSet()) {
VisitCompare(selector, opcode, g.UseRegister(right),
g.UseImmediate(left), cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(right),
g.UseRegister(left), cont);
}
break;
case kSignedLessThan:
case kSignedGreaterThanOrEqual:
case kUnsignedLessThan:
......
src/compiler/mips64/code-generator-mips64.cc
View file @ 0c5c4795
......@@ -1046,19 +1046,10 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
if (instr->arch_opcode() == kMips64Tst) {
cc = FlagsConditionToConditionTst(condition);
__ And(kScratchReg, i.InputRegister(0), i.InputOperand(1));
__ xori(result, zero_reg, 1); // Create 1 for true.
if (kArchVariant == kMips64r6) {
if (cc == eq) {
__ seleqz(result, result, kScratchReg);
} else {
__ selnez(result, result, kScratchReg);
}
} else {
if (cc == eq) {
__ Movn(result, zero_reg, kScratchReg);
} else {
__ Movz(result, zero_reg, kScratchReg);
}
__ Sltu(result, zero_reg, kScratchReg);
if (cc == eq) {
// Sltu produces 0 for equality, invert the result.
__ xori(result, result, 1);
}
return;
} else if (instr->arch_opcode() == kMips64Dadd ||
......@@ -1078,20 +1069,18 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
case ne: {
Register left = i.InputRegister(0);
Operand right = i.InputOperand(1);
__ Dsubu(kScratchReg, left, right);
__ xori(result, zero_reg, 1);
if (kArchVariant == kMips64r6) {
if (cc == eq) {
__ seleqz(result, result, kScratchReg);
} else {
__ selnez(result, result, kScratchReg);
}
Register select;
if (instr->InputAt(1)->IsImmediate() && right.immediate() == 0) {
// Pass left operand if right is zero.
select = left;
} else {
if (cc == eq) {
__ Movn(result, zero_reg, kScratchReg);
} else {
__ Movz(result, zero_reg, kScratchReg);
}
__ Dsubu(kScratchReg, left, right);
select = kScratchReg;
}
__ Sltu(result, zero_reg, select);
if (cc == eq) {
// Sltu produces 0 for equality, invert the result.
__ xori(result, result, 1);
}
} break;
case lt:
......
src/compiler/mips64/instruction-selector-mips64.cc
View file @ 0c5c4795
......@@ -1019,6 +1019,16 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
// Match immediates on left or right side of comparison.
if (g.CanBeImmediate(right, opcode)) {
switch (cont->condition()) {
case kEqual:
case kNotEqual:
if (cont->IsSet()) {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseImmediate(right), cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseRegister(right), cont);
}
break;
case kSignedLessThan:
case kSignedGreaterThanOrEqual:
case kUnsignedLessThan:
......@@ -1033,6 +1043,16 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
} else if (g.CanBeImmediate(left, opcode)) {
if (!commutative) cont->Commute();
switch (cont->condition()) {
case kEqual:
case kNotEqual:
if (cont->IsSet()) {
VisitCompare(selector, opcode, g.UseRegister(right),
g.UseImmediate(left), cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(right),
g.UseRegister(left), cont);
}
break;
case kSignedLessThan:
case kSignedGreaterThanOrEqual:
case kUnsignedLessThan:
......
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