s390x: Implement Store LE version

Change-Id: I5422d4288eebedac86077a42286231e5c225232d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2642877
Commit-Queue: Junliang Yan <junyan@redhat.com>
Reviewed-by: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#72232}

src/codegen/s390/macro-assembler-s390.cc

@@ -3439,19 +3439,9 @@ void TurboAssembler::StoreU64(Register src, const MemOperand& mem,
     DCHECK(scratch != no_reg);
     DCHECK(scratch != r0);
     mov(scratch, Operand(mem.offset()));
-#if V8_TARGET_ARCH_S390X
     stg(src, MemOperand(mem.rb(), scratch));
-#else
-    st(src, MemOperand(mem.rb(), scratch));
-#endif
   } else {
-#if V8_TARGET_ARCH_S390X
     stg(src, mem);
-#else
-    // StoreU32 will try to generate ST if offset fits, otherwise
-    // it'll generate STY.
-    StoreU32(src, mem);
-#endif
   }
 }
 
@@ -3464,11 +3454,7 @@ void TurboAssembler::StoreU64(const MemOperand& mem, const Operand& opnd,
   // Try to use MVGHI/MVHI
   if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT) && is_uint12(mem.offset()) &&
       mem.getIndexRegister() == r0 && is_int16(opnd.immediate())) {
-#if V8_TARGET_ARCH_S390X
     mvghi(mem, opnd);
-#else
-    mvhi(mem, opnd);
-#endif
   } else {
     mov(scratch, opnd);
     StoreU64(scratch, mem);
@@ -3715,6 +3701,70 @@ void TurboAssembler::LoadF32LE(DoubleRegister dst, const MemOperand& opnd,
   ldgr(dst, scratch);
 }
 
+void TurboAssembler::StoreU64LE(Register src, const MemOperand& mem,
+                                Register scratch) {
+  if (!is_int20(mem.offset())) {
+    DCHECK(scratch != no_reg);
+    DCHECK(scratch != r0);
+    mov(scratch, Operand(mem.offset()));
+    strvg(src, MemOperand(mem.rb(), scratch));
+  } else {
+    strvg(src, mem);
+  }
+}
+
+void TurboAssembler::StoreU32LE(Register src, const MemOperand& mem,
+                                Register scratch) {
+  if (!is_int20(mem.offset())) {
+    DCHECK(scratch != no_reg);
+    DCHECK(scratch != r0);
+    mov(scratch, Operand(mem.offset()));
+    strv(src, MemOperand(mem.rb(), scratch));
+  } else {
+    strv(src, mem);
+  }
+}
+
+void TurboAssembler::StoreU16LE(Register src, const MemOperand& mem,
+                                Register scratch) {
+  if (!is_int20(mem.offset())) {
+    DCHECK(scratch != no_reg);
+    DCHECK(scratch != r0);
+    mov(scratch, Operand(mem.offset()));
+    strvh(src, MemOperand(mem.rb(), scratch));
+  } else {
+    strvh(src, mem);
+  }
+}
+
+void TurboAssembler::StoreF64LE(DoubleRegister src, const MemOperand& opnd,
+                                Register scratch) {
+  DCHECK(!is_int20(mem.offset()));
+  lgdr(scratch, src);
+  strvg(scratch, opnd);
+}
+
+void TurboAssembler::StoreF32LE(DoubleRegister src, const MemOperand& opnd,
+                                Register scratch) {
+  DCHECK(!is_int20(mem.offset()));
+  lgdr(scratch, src);
+  ShiftRightU64(scratch, scratch, Operand(32));
+  strv(scratch, opnd);
+}
+
+void TurboAssembler::StoreV128LE(Simd128Register src, const MemOperand& mem,
+                                 Register scratch1, Register scratch2) {
+  if (CpuFeatures::IsSupported(VECTOR_ENHANCE_FACILITY_2)) {
+    vstbr(src, mem, Condition(4));
+  } else {
+    vlgv(scratch1, src, MemOperand(r0, 1), Condition(3));
+    vlgv(scratch2, src, MemOperand(r0, 0), Condition(3));
+    strvg(scratch1, mem);
+    strvg(scratch2,
+          MemOperand(mem.rx(), mem.rb(), mem.offset() + kSystemPointerSize));
+  }
+}
+
 #else
 void TurboAssembler::LoadU64LE(Register dst, const MemOperand& mem,
                                Register scratch) {
@@ -3757,6 +3807,36 @@ void TurboAssembler::LoadF32LE(DoubleRegister dst, const MemOperand& opnd,
   LoadF32(dst, opnd);
 }
 
+void TurboAssembler::StoreU64LE(Register src, const MemOperand& mem,
+                                Register scratch) {
+  StoreU64(src, mem, scratch);
+}
+
+void TurboAssembler::StoreU32LE(Register src, const MemOperand& mem,
+                                Register scratch) {
+  StoreU32(src, mem, scratch);
+}
+
+void TurboAssembler::StoreU16LE(Register src, const MemOperand& mem,
+                                Register scratch) {
+  StoreU16(src, mem, scratch);
+}
+
+void TurboAssembler::StoreF64LE(DoubleRegister src, const MemOperand& opnd,
+                                Register scratch) {
+  StoreF64(src, opnd);
+}
+
+void TurboAssembler::StoreF32LE(DoubleRegister src, const MemOperand& opnd,
+                                Register scratch) {
+  StoreF32(src, opnd);
+}
+
+void TurboAssembler::StoreV128LE(Simd128Register src, const MemOperand& mem,
+                                 Register scratch1, Register scratch2) {
+  StoreV128(src, mem, scratch1);
+}
+
 #endif
 
 // Load And Test (Reg <- Reg)

src/codegen/s390/macro-assembler-s390.h

@@ -364,6 +364,29 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void LoadAndTest32(Register dst, const MemOperand& opnd);
   void LoadAndTestP(Register dst, const MemOperand& opnd);
 
+  // Store
+  void StoreU64(const MemOperand& mem, const Operand& opnd,
+                Register scratch = no_reg);
+  void StoreU64(Register src, const MemOperand& mem, Register scratch = no_reg);
+  void StoreU32(Register src, const MemOperand& mem, Register scratch = no_reg);
+
+  void StoreU16(Register src, const MemOperand& mem, Register scratch = r0);
+  void StoreU8(Register src, const MemOperand& mem, Register scratch = r0);
+  void StoreF64(DoubleRegister dst, const MemOperand& opnd);
+  void StoreF32(DoubleRegister dst, const MemOperand& opnd);
+  void StoreV128(Simd128Register src, const MemOperand& mem, Register scratch);
+
+  // Store LE
+  void StoreU64LE(Register src, const MemOperand& mem,
+                  Register scratch = no_reg);
+  void StoreU32LE(Register src, const MemOperand& mem,
+                  Register scratch = no_reg);
+
+  void StoreU16LE(Register src, const MemOperand& mem, Register scratch = r0);
+  void StoreF64LE(DoubleRegister src, const MemOperand& opnd, Register scratch);
+  void StoreF32LE(DoubleRegister src, const MemOperand& opnd, Register scratch);
+  void StoreV128LE(Simd128Register src, const MemOperand& mem,
+                   Register scratch1, Register scratch2);
 
   void AddFloat32(DoubleRegister dst, const MemOperand& opnd,
                   DoubleRegister scratch);
@@ -390,18 +413,6 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void LoadPositiveP(Register result, Register input);
   void LoadPositive32(Register result, Register input);
 
-  // Store
-  void StoreU64(Register src, const MemOperand& mem, Register scratch = no_reg);
-  void StoreU64(const MemOperand& mem, const Operand& opnd,
-                Register scratch = no_reg);
-  void StoreU32(Register src, const MemOperand& mem, Register scratch = no_reg);
-
-  void StoreU16(Register src, const MemOperand& mem, Register scratch = r0);
-  void StoreU8(Register src, const MemOperand& mem, Register scratch = r0);
-  void StoreF64(DoubleRegister dst, const MemOperand& opnd);
-  void StoreF32(DoubleRegister dst, const MemOperand& opnd);
-  void StoreV128(Simd128Register src, const MemOperand& mem, Register scratch);
-
   void Branch(Condition c, const Operand& opnd);
   void BranchOnCount(Register r1, Label* l);