Commit 0b5ce79d authored by Zhao Jiazhong's avatar Zhao Jiazhong Committed by Commit Bot

[mips][wasm-simd][liftoff] Implement add for i32x4, i16x8, f32x4.

Port fd735e84
https://crrev.com/c/2067631

Change-Id: I720c4e218ea7a6088c61c2411c7c74e636f0772a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2089228Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Reviewed-by: 's avatarZhi An Ng <zhin@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66619}
parent 81d4425e
......@@ -1548,6 +1548,14 @@ void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst,
bailout(kSimd, "emit_f32x4_splat");
}
void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister rhs,
LiftoffRegister lhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_f32x4_add");
}
void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1564,6 +1572,14 @@ void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst,
bailout(kSimd, "emit_i32x4_splat");
}
void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister rhs,
LiftoffRegister lhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i32x4_add");
}
void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1572,6 +1588,14 @@ void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst,
bailout(kSimd, "emit_i16x8_splat");
}
void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister rhs,
LiftoffRegister lhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i16x8_add");
}
void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......
......@@ -1340,6 +1340,14 @@ void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst,
bailout(kSimd, "emit_f32x4_splat");
}
void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister rhs,
LiftoffRegister lhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_f32x4_add");
}
void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1356,6 +1364,14 @@ void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst,
bailout(kSimd, "emit_i32x4_splat");
}
void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister rhs,
LiftoffRegister lhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i32x4_add");
}
void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......@@ -1364,6 +1380,14 @@ void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst,
bailout(kSimd, "emit_i16x8_splat");
}
void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister rhs,
LiftoffRegister lhs) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
// CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming
// 3a4000 support MSA.
bailout(kSimd, "emit_i16x8_add");
}
void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst,
LiftoffRegister src) {
// TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment