Commit 0aee27f5 authored by David Carlier's avatar David Carlier Committed by Commit Bot

Porting icache generation for ARM to FreeBSD

Adaptation coming from the ports for upstream purposes.

Change-Id: Ia1d0d6dabfd10d5840084bb90814c33ea9fb6aa8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1906373Reviewed-by: 's avatarUlan Degenbaev <ulan@chromium.org>
Reviewed-by: 's avatarRoss McIlroy <rmcilroy@chromium.org>
Commit-Queue: Ulan Degenbaev <ulan@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65213}
parent 4a5a1daa
......@@ -7,6 +7,9 @@
#ifdef __QNXNTO__
#include <sys/mman.h> // for cache flushing.
#undef MAP_TYPE // NOLINT
#elif V8_OS_FREEBSD
#include <machine/sysarch.h> // for cache flushing
#include <sys/types.h>
#else
#include <sys/syscall.h> // for cache flushing.
#endif
......@@ -25,6 +28,10 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
#if !defined(USE_SIMULATOR)
#if V8_OS_QNX
msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
#elif V8_OS_FREEBSD
struct arm_sync_icache_args args = {
.addr = reinterpret_cast<uintptr_t>(start), .len = size};
sysarch(ARM_SYNC_ICACHE, reinterpret_cast<void*>(&args));
#else
register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start);
register uint32_t end asm("r1") = beg + size;
......
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