Commit 0a5a8e88 authored by feng@chromium.org's avatar feng@chromium.org

Fix and cleanup ARM port:

1) removed unused function, PcStoreOffset;
2) use macro instruction, Jump, when branching from JS code to C code.

This CL replaces http://codereview.chromium.org/53039/show, per our discussion.

Review URL: http://codereview.chromium.org/42610

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1614 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent 03419c83
......@@ -84,55 +84,6 @@ CRegister cr14 = { 14 };
CRegister cr15 = { 15 };
// In order to determine the pc store offset, we execute a small code sequence.
// See ARM Architecture Reference Manual section A-2.4.3
// Note that 'str pc, [sp]' and 'stmia sp, {pc}' were using different offsets
// under the QEMU emulator (now fixed), so we are careful to test the actual
// instruction we are interested in (stmia).
int PcStoreOffset() {
#if !defined(__arm__)
// Building an ARM emulator based target. The emulator is wired for 8 byte
// pc offsets as is the default in the spec.
static int pc_store_offset = 8;
#elif defined(__arm__) && !defined(__thumb__)
// __arm__ may be defined in thumb mode.
static int pc_store_offset = -1;
asm volatile(
"sub sp, sp, #4 \n\t"
"sub r1, pc, #4 \n\t"
"stmia sp, {pc} \n\t"
"ldr r0, [sp] \n\t"
"add sp, sp, #4 \n\t"
"sub %0, r0, r1 \n\t"
: "=r" (pc_store_offset) : : "r0", "r1", "memory");
#elif defined(__thumb__)
static int pc_store_offset = -1;
asm volatile(
"@ Enter ARM Mode \n\t"
"adr r2, 1f \n\t"
"bx r2 \n\t"
".ALIGN 4 \n\t"
".ARM \n"
"1: sub sp, sp, #4 \n\t"
"sub r1, pc, #4 \n\t"
"stmia sp, {pc} \n\t"
"ldr r0, [sp] \n\t"
"add sp, sp, #4 \n\t"
"sub %0, r0, r1 \n"
"@ Enter THUMB Mode\n\t"
"adr r2, 2f+1 \n\t"
"bx r2 \n\t"
".THUMB \n"
"2: \n\t"
: "=r" (pc_store_offset) : : "r0", "r1", "r2", "memory");
#else
#error unsupported architecture
#endif
ASSERT(pc_store_offset == 8 || pc_store_offset == 12);
return pc_store_offset;
}
// -----------------------------------------------------------------------------
// Implementation of RelocInfo
......
......@@ -222,10 +222,6 @@ enum Hint { no_hint };
inline Hint NegateHint(Hint ignored) { return no_hint; }
// The pc store offset may be 8 or 12 depending on the processor implementation.
int PcStoreOffset();
// -----------------------------------------------------------------------------
// Addressing modes and instruction variants
......
......@@ -4858,7 +4858,7 @@ void CEntryStub::GenerateCore(MacroAssembler* masm,
// Notify the simulator of the transition to C code.
__ swi(assembler::arm::call_rt_r5);
#else /* !defined(__arm__) */
__ mov(pc, Operand(r5));
__ Jump(r5);
#endif /* !defined(__arm__) */
if (always_allocate) {
......
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