MIPS: [turbofan] Support Float[32|64]Min and Float[32|64]Max.

MIPS64r6 and MIPS32r6 support for min and max and Float64Max machine operators.

BUG=

Review URL: https://codereview.chromium.org/1027193002

Cr-Commit-Position: refs/heads/master@{#28471}

src/compiler/mips/code-generator-mips.cc

@@ -622,6 +622,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ sqrt_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
       break;
     }
+    case kMipsMaxS:
+      __ max_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
+    case kMipsMinS:
+      __ min_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
     case kMipsCmpD:
       // Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
       break;
@@ -663,6 +671,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ sqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
       break;
     }
+    case kMipsMaxD:
+      __ max_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
+    case kMipsMinD:
+      __ min_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
     case kMipsFloat64RoundDown: {
       ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(floor_l_d, Floor);
       break;

src/compiler/mips/instruction-codes-mips.h

@@ -42,6 +42,8 @@ namespace compiler {
   V(MipsModS)                      \
   V(MipsAbsS)                      \
   V(MipsSqrtS)                     \
+  V(MipsMaxS)                      \
+  V(MipsMinS)                      \
   V(MipsCmpD)                      \
   V(MipsAddD)                      \
   V(MipsSubD)                      \
@@ -50,6 +52,8 @@ namespace compiler {
   V(MipsModD)                      \
   V(MipsAbsD)                      \
   V(MipsSqrtD)                     \
+  V(MipsMaxD)                      \
+  V(MipsMinD)                      \
   V(MipsFloat64RoundDown)          \
   V(MipsFloat64RoundTruncate)      \
   V(MipsFloat64RoundUp)            \

src/compiler/mips/instruction-selector-mips.cc

@@ -452,16 +452,28 @@ void InstructionSelector::VisitFloat64Mod(Node* node) {
 }
 
 
-void InstructionSelector::VisitFloat32Max(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat32Max(Node* node) {
+  DCHECK(kArchVariant == kMips32r6);
+  VisitRRR(this, kMipsMaxS, node);
+}
 
 
-void InstructionSelector::VisitFloat64Max(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Max(Node* node) {
+  DCHECK(kArchVariant == kMips32r6);
+  VisitRRR(this, kMipsMaxD, node);
+}
 
 
-void InstructionSelector::VisitFloat32Min(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat32Min(Node* node) {
+  DCHECK(kArchVariant == kMips32r6);
+  VisitRRR(this, kMipsMinS, node);
+}
 
 
-void InstructionSelector::VisitFloat64Min(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Min(Node* node) {
+  DCHECK(kArchVariant == kMips32r6);
+  VisitRRR(this, kMipsMinD, node);
+}
 
 
 void InstructionSelector::VisitFloat32Abs(Node* node) {
@@ -1059,6 +1071,12 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags;
+  if (IsMipsArchVariant(kMips32r6)) {
+    flags |= MachineOperatorBuilder::kFloat32Max |
+             MachineOperatorBuilder::kFloat32Min |
+             MachineOperatorBuilder::kFloat64Max |
+             MachineOperatorBuilder::kFloat64Min;
+  }
   if ((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
       IsFp64Mode()) {
     flags |= MachineOperatorBuilder::kFloat64RoundDown |

src/compiler/mips64/code-generator-mips64.cc

@@ -684,6 +684,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ sqrt_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
       break;
     }
+    case kMips64MaxS:
+      __ max_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
+    case kMips64MinS:
+      __ min_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
     case kMips64CmpD:
       // Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
       break;
@@ -725,6 +733,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ sqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
       break;
     }
+    case kMips64MaxD:
+      __ max_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
+    case kMips64MinD:
+      __ min_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+               i.InputDoubleRegister(1));
+      break;
     case kMips64Float64RoundDown: {
       ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(floor_l_d, Floor);
       break;

src/compiler/mips64/instruction-codes-mips64.h

@@ -53,6 +53,8 @@ namespace compiler {
   V(Mips64ModS)                     \
   V(Mips64AbsS)                     \
   V(Mips64SqrtS)                    \
+  V(Mips64MaxS)                     \
+  V(Mips64MinS)                     \
   V(Mips64CmpD)                     \
   V(Mips64AddD)                     \
   V(Mips64SubD)                     \
@@ -61,6 +63,8 @@ namespace compiler {
   V(Mips64ModD)                     \
   V(Mips64AbsD)                     \
   V(Mips64SqrtD)                    \
+  V(Mips64MaxD)                     \
+  V(Mips64MinD)                     \
   V(Mips64Float64RoundDown)         \
   V(Mips64Float64RoundTruncate)     \
   V(Mips64Float64RoundUp)           \

src/compiler/mips64/instruction-selector-mips64.cc

@@ -601,16 +601,28 @@ void InstructionSelector::VisitFloat64Mod(Node* node) {
 }
 
 
-void InstructionSelector::VisitFloat32Max(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat32Max(Node* node) {
+  DCHECK(kArchVariant == kMips64r6);
+  VisitRRR(this, kMips64MaxS, node);
+}
 
 
-void InstructionSelector::VisitFloat64Max(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Max(Node* node) {
+  DCHECK(kArchVariant == kMips64r6);
+  VisitRRR(this, kMips64MaxD, node);
+}
 
 
-void InstructionSelector::VisitFloat32Min(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat32Min(Node* node) {
+  DCHECK(kArchVariant == kMips64r6);
+  VisitRRR(this, kMips64MinS, node);
+}
 
 
-void InstructionSelector::VisitFloat64Min(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Min(Node* node) {
+  DCHECK(kArchVariant == kMips64r6);
+  VisitRRR(this, kMips64MinD, node);
+}
 
 
 void InstructionSelector::VisitFloat32Abs(Node* node) {
@@ -1271,8 +1283,16 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
-  return MachineOperatorBuilder::kFloat64RoundDown |
-         MachineOperatorBuilder::kFloat64RoundTruncate;
+  MachineOperatorBuilder::Flags flags =
+      MachineOperatorBuilder::kFloat64RoundDown |
+      MachineOperatorBuilder::kFloat64RoundTruncate;
+  if (kArchVariant == kMips64r6) {
+    flags |= MachineOperatorBuilder::kFloat32Max |
+             MachineOperatorBuilder::kFloat32Min |
+             MachineOperatorBuilder::kFloat64Max |
+             MachineOperatorBuilder::kFloat64Min;
+  }
+  return flags;
 }
 
 }  // namespace compiler