Commit 086ec2bd authored by ahaas's avatar ahaas Committed by Commit bot

[arm64] The ubfx instruction can be used with a mask-width=64

The code-generator used i.InputInt6 to get the mask-width from the
instruction. However, thereby 64 got wrapped to 0, which is an invalid
mask width. I changed the i.InputInt6 to an i.InputInt32, which should
be okay because the mask-width comes from base::bits::CountPopulation64.

BUG=v8:6122
R=bmeurer@chromium.org, v8-arm-ports@googlegroups.com

Review-Url: https://codereview.chromium.org/2755373002
Cr-Commit-Position: refs/heads/master@{#43927}
parent 515c7a4e
......@@ -1191,11 +1191,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
case kArm64Ubfx:
__ Ubfx(i.OutputRegister(), i.InputRegister(0), i.InputInt6(1),
i.InputInt6(2));
i.InputInt32(2));
break;
case kArm64Ubfx32:
__ Ubfx(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),
i.InputInt5(2));
i.InputInt32(2));
break;
case kArm64Ubfiz32:
__ Ubfiz(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),
......
......@@ -6746,6 +6746,15 @@ TEST(Regression6046a) {
CHECK_EQ(0, m.Call());
}
TEST(Regression6122) {
BufferedRawMachineAssemblerTester<int64_t> m;
m.Return(m.Word64Shr(m.Word64And(m.Int64Constant(59), m.Int64Constant(-1)),
m.Int64Constant(0)));
CHECK_EQ(59, m.Call());
}
#endif // V8_TARGET_ARCH_64_BIT
TEST(Regression6046b) {
BufferedRawMachineAssemblerTester<int32_t> m;
m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(0), m.Int32Constant(0)),
......@@ -6753,7 +6762,12 @@ TEST(Regression6046b) {
CHECK_EQ(0, m.Call());
}
#endif // V8_TARGET_ARCH_64_BIT
TEST(Regression6122b) {
BufferedRawMachineAssemblerTester<int32_t> m;
m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(59), m.Int32Constant(-1)),
m.Int32Constant(0)));
CHECK_EQ(59, m.Call());
}
TEST(Regression6028) {
BufferedRawMachineAssemblerTester<int32_t> m;
......
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