Skip to content

V
V8
Commit 065b2374 authored by jacob.bramley's avatar jacob.bramley Committed by Commit bot
Browse files
Options

Reland [arm64][turbofan]: Handle any immediate shift. 

With this patch, we can generate simple immediate-shift instructions for
immediates outside the range "0 <= imm < width". Several related
instruction selectors have also been updated accordingly.

Example of generated code:

    ---- Before ---         ---- After ----
    movz w0, #33            lsr w0, w1, #1
    lsr  w0, w1, w0

BUG=

Review URL: https://codereview.chromium.org/1179893003

Cr-Commit-Position: refs/heads/master@{#28977}
parent b702cd97
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 139 additions and 103 deletions
src/compiler/arm64/code-generator-arm64.cc
View file @ 065b2374
......@@ -331,16 +331,17 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
} while (0)
#define ASSEMBLE_SHIFT(asm_instr, width) \
do { \
if (instr->InputAt(1)->IsRegister()) { \
__ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), \
i.InputRegister##width(1)); \
} else { \
int imm = \
static_cast<int>(i.InputOperand##width(1).immediate().value()); \
__ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), imm); \
} \
#define ASSEMBLE_SHIFT(asm_instr, width) \
do { \
if (instr->InputAt(1)->IsRegister()) { \
__ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), \
i.InputRegister##width(1)); \
} else { \
uint32_t imm = \
static_cast<uint32_t>(i.InputOperand##width(1).ImmediateValue()); \
__ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), \
imm % (width)); \
} \
} while (0)
......
test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
View file @ 065b2374
......@@ -642,7 +642,9 @@ TEST_F(InstructionSelectorTest, AddShiftByImmediateOnLeft) {
if (shift.mi.machine_type != kMachInt32) continue;
if (shift.mi.arch_opcode == kArm64Ror32) continue;
TRACED_FORRANGE(int, imm, 0, 31) {
// The available shift operand range is `0 <= imm < 32`, but we also test
// that immediates outside this range are handled properly (modulo-32).
TRACED_FORRANGE(int, imm, -32, 63) {
StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
m.Return((m.Int32Add)(
(m.*shift.mi.constructor)(m.Parameter(1), m.Int32Constant(imm)),
......@@ -663,7 +665,9 @@ TEST_F(InstructionSelectorTest, AddShiftByImmediateOnLeft) {
if (shift.mi.machine_type != kMachInt64) continue;
if (shift.mi.arch_opcode == kArm64Ror) continue;
TRACED_FORRANGE(int, imm, 0, 63) {
// The available shift operand range is `0 <= imm < 64`, but we also test
// that immediates outside this range are handled properly (modulo-64).
TRACED_FORRANGE(int, imm, -64, 127) {
StreamBuilder m(this, kMachInt64, kMachInt64, kMachInt64);
m.Return((m.Int64Add)(
(m.*shift.mi.constructor)(m.Parameter(1), m.Int64Constant(imm)),
......@@ -2394,14 +2398,17 @@ TEST_F(InstructionSelectorTest, Word64XorMinusOneWithParameter) {
TEST_F(InstructionSelectorTest, Word32ShrWithWord32AndWithImmediate) {
TRACED_FORRANGE(int32_t, lsb, 1, 31) {
// The available shift operand range is `0 <= imm < 32`, but we also test
// that immediates outside this range are handled properly (modulo-32).
TRACED_FORRANGE(int32_t, shift, -32, 63) {
int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
uint32_t jnk = rng()->NextInt();
jnk >>= 32 - lsb;
jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
StreamBuilder m(this, kMachInt32, kMachInt32);
m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)),
m.Int32Constant(lsb)));
m.Int32Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
......@@ -2410,14 +2417,15 @@ TEST_F(InstructionSelectorTest, Word32ShrWithWord32AndWithImmediate) {
EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
}
}
TRACED_FORRANGE(int32_t, lsb, 1, 31) {
TRACED_FORRANGE(int32_t, shift, -32, 63) {
int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
uint32_t jnk = rng()->NextInt();
jnk >>= 32 - lsb;
jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
StreamBuilder m(this, kMachInt32, kMachInt32);
m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)),
m.Int32Constant(lsb)));
m.Int32Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
......@@ -2430,15 +2438,18 @@ TEST_F(InstructionSelectorTest, Word32ShrWithWord32AndWithImmediate) {
TEST_F(InstructionSelectorTest, Word64ShrWithWord64AndWithImmediate) {
TRACED_FORRANGE(int32_t, lsb, 1, 63) {
// The available shift operand range is `0 <= imm < 64`, but we also test
// that immediates outside this range are handled properly (modulo-64).
TRACED_FORRANGE(int32_t, shift, -64, 127) {
int32_t lsb = shift & 0x3f;
TRACED_FORRANGE(int32_t, width, 1, 64 - lsb) {
uint64_t jnk = rng()->NextInt64();
jnk >>= 64 - lsb;
jnk = (lsb > 0) ? (jnk >> (64 - lsb)) : 0;
uint64_t msk =
((V8_UINT64_C(0xffffffffffffffff) >> (64 - width)) << lsb) | jnk;
StreamBuilder m(this, kMachInt64, kMachInt64);
m.Return(m.Word64Shr(m.Word64And(m.Parameter(0), m.Int64Constant(msk)),
m.Int64Constant(lsb)));
m.Int64Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx, s[0]->arch_opcode());
......@@ -2447,15 +2458,16 @@ TEST_F(InstructionSelectorTest, Word64ShrWithWord64AndWithImmediate) {
EXPECT_EQ(width, s.ToInt64(s[0]->InputAt(2)));
}
}
TRACED_FORRANGE(int32_t, lsb, 1, 63) {
TRACED_FORRANGE(int32_t, shift, -64, 127) {
int32_t lsb = shift & 0x3f;
TRACED_FORRANGE(int32_t, width, 1, 64 - lsb) {
uint64_t jnk = rng()->NextInt64();
jnk >>= 64 - lsb;
jnk = (lsb > 0) ? (jnk >> (64 - lsb)) : 0;
uint64_t msk =
((V8_UINT64_C(0xffffffffffffffff) >> (64 - width)) << lsb) | jnk;
StreamBuilder m(this, kMachInt64, kMachInt64);
m.Return(m.Word64Shr(m.Word64And(m.Int64Constant(msk), m.Parameter(0)),
m.Int64Constant(lsb)));
m.Int64Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx, s[0]->arch_opcode());
......@@ -2468,11 +2480,14 @@ TEST_F(InstructionSelectorTest, Word64ShrWithWord64AndWithImmediate) {
TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
TRACED_FORRANGE(int32_t, lsb, 1, 31) {
// The available shift operand range is `0 <= imm < 32`, but we also test
// that immediates outside this range are handled properly (modulo-32).
TRACED_FORRANGE(int32_t, shift, -32, 63) {
int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 31) {
uint32_t msk = (1 << width) - 1;
StreamBuilder m(this, kMachInt32, kMachInt32);
m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)),
m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(shift)),
m.Int32Constant(msk)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
......@@ -2483,12 +2498,14 @@ TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
EXPECT_EQ(actual_width, s.ToInt32(s[0]->InputAt(2)));
}
}
TRACED_FORRANGE(int32_t, lsb, 1, 31) {
TRACED_FORRANGE(int32_t, shift, -32, 63) {
int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 31) {
uint32_t msk = (1 << width) - 1;
StreamBuilder m(this, kMachInt32, kMachInt32);
m.Return(m.Word32And(m.Int32Constant(msk),
m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb))));
m.Return(
m.Word32And(m.Int32Constant(msk),
m.Word32Shr(m.Parameter(0), m.Int32Constant(shift))));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
......@@ -2502,11 +2519,14 @@ TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
TEST_F(InstructionSelectorTest, Word64AndWithImmediateWithWord64Shr) {
TRACED_FORRANGE(int64_t, lsb, 1, 63) {
// The available shift operand range is `0 <= imm < 64`, but we also test
// that immediates outside this range are handled properly (modulo-64).
TRACED_FORRANGE(int64_t, shift, -64, 127) {
int64_t lsb = shift & 0x3f;
TRACED_FORRANGE(int64_t, width, 1, 63) {
uint64_t msk = (V8_UINT64_C(1) << width) - 1;
StreamBuilder m(this, kMachInt64, kMachInt64);
m.Return(m.Word64And(m.Word64Shr(m.Parameter(0), m.Int64Constant(lsb)),
m.Return(m.Word64And(m.Word64Shr(m.Parameter(0), m.Int64Constant(shift)),
m.Int64Constant(msk)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
......@@ -2517,12 +2537,14 @@ TEST_F(InstructionSelectorTest, Word64AndWithImmediateWithWord64Shr) {
EXPECT_EQ(actual_width, s.ToInt64(s[0]->InputAt(2)));
}
}
TRACED_FORRANGE(int64_t, lsb, 1, 63) {
TRACED_FORRANGE(int64_t, shift, -64, 127) {
int64_t lsb = shift & 0x3f;
TRACED_FORRANGE(int64_t, width, 1, 63) {
uint64_t msk = (V8_UINT64_C(1) << width) - 1;
StreamBuilder m(this, kMachInt64, kMachInt64);
m.Return(m.Word64And(m.Int64Constant(msk),
m.Word64Shr(m.Parameter(0), m.Int64Constant(lsb))));
m.Return(
m.Word64And(m.Int64Constant(msk),
m.Word64Shr(m.Parameter(0), m.Int64Constant(shift))));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx, s[0]->arch_opcode());
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment