[riscv64] Fix RvvGts emit wrong instr

Change-Id: Icd2ed5c6e54dec208afa9a09b0e4fe9bcd410687
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3167438
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#76898}

src/compiler/backend/riscv64/code-generator-riscv64.cc

@@ -2156,12 +2156,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kRiscvI32x4GtS: {
-      __ WasmRvvGtU(i.OutputSimd128Register(), i.InputSimd128Register(0),
+      __ WasmRvvGtS(i.OutputSimd128Register(), i.InputSimd128Register(0),
                     i.InputSimd128Register(1), E32, m1);
       break;
     }
     case kRiscvI64x2GtS: {
-      __ WasmRvvGtU(i.OutputSimd128Register(), i.InputSimd128Register(0),
+      __ WasmRvvGtS(i.OutputSimd128Register(), i.InputSimd128Register(0),
                     i.InputSimd128Register(1), E64, m1);
       break;
     }