Revert "Revert of [Atomics] Implement ldaxr/stlxr instructions in ARM64...

Revert "Revert of [Atomics] Implement ldaxr/stlxr instructions in ARM64 simulator (patchset #8 id:140001 of https://codereview.chromium.org/2711473002/ )"

This reverts commit 2362f869.

BUG=v8:4614

Review-Url: https://codereview.chromium.org/2720133004
Cr-Commit-Position: refs/heads/master@{#43467}

src/arm64/constants-arm64.h

@@ -199,7 +199,14 @@ const unsigned kFloatExponentBits = 8;
   V_(SysOp1, 18, 16, Bits)                              \
   V_(SysOp2, 7, 5, Bits)                                \
   V_(CRn, 15, 12, Bits)                                 \
-  V_(CRm, 11, 8, Bits)
+  V_(CRm, 11, 8, Bits)                                  \
+                                                        \
+  /* Load-/store-exclusive */                           \
+  V_(LoadStoreXLoad, 22, 22, Bits)                      \
+  V_(LoadStoreXNotExclusive, 23, 23, Bits)              \
+  V_(LoadStoreXAcquireRelease, 15, 15, Bits)            \
+  V_(LoadStoreXSizeLog2, 31, 30, Bits)                  \
+  V_(LoadStoreXPair, 21, 21, Bits)
 
 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_)                                    \
 /* NZCV */                                                                     \

src/arm64/simulator-arm64.h

@@ -865,6 +865,97 @@ class Simulator : public DecoderVisitor {
   char* last_debugger_input() { return last_debugger_input_; }
   char* last_debugger_input_;
 
+  // Synchronization primitives. See ARM DDI 0487A.a, B2.10. Pair types not
+  // implemented.
+  enum class MonitorAccess {
+    Open,
+    Exclusive,
+  };
+
+  enum class TransactionSize {
+    None = 0,
+    Byte = 1,
+    HalfWord = 2,
+    Word = 4,
+  };
+
+  TransactionSize get_transaction_size(unsigned size);
+
+  // The least-significant bits of the address are ignored. The number of bits
+  // is implementation-defined, between 3 and 11. See ARM DDI 0487A.a, B2.10.3.
+  static const uintptr_t kExclusiveTaggedAddrMask = ~((1 << 11) - 1);
+
+  class LocalMonitor {
+   public:
+    LocalMonitor();
+
+    // These functions manage the state machine for the local monitor, but do
+    // not actually perform loads and stores. NotifyStoreExcl only returns
+    // true if the exclusive store is allowed; the global monitor will still
+    // have to be checked to see whether the memory should be updated.
+    void NotifyLoad(uintptr_t addr);
+    void NotifyLoadExcl(uintptr_t addr, TransactionSize size);
+    void NotifyStore(uintptr_t addr);
+    bool NotifyStoreExcl(uintptr_t addr, TransactionSize size);
+
+   private:
+    void Clear();
+
+    MonitorAccess access_state_;
+    uintptr_t tagged_addr_;
+    TransactionSize size_;
+  };
+
+  class GlobalMonitor {
+   public:
+    GlobalMonitor();
+
+    class Processor {
+     public:
+      Processor();
+
+     private:
+      friend class GlobalMonitor;
+      // These functions manage the state machine for the global monitor, but do
+      // not actually perform loads and stores.
+      void Clear_Locked();
+      void NotifyLoadExcl_Locked(uintptr_t addr);
+      void NotifyStore_Locked(uintptr_t addr, bool is_requesting_processor);
+      bool NotifyStoreExcl_Locked(uintptr_t addr, bool is_requesting_processor);
+
+      MonitorAccess access_state_;
+      uintptr_t tagged_addr_;
+      Processor* next_;
+      Processor* prev_;
+      // A stxr can fail due to background cache evictions. Rather than
+      // simulating this, we'll just occasionally introduce cases where an
+      // exclusive store fails. This will happen once after every
+      // kMaxFailureCounter exclusive stores.
+      static const int kMaxFailureCounter = 5;
+      int failure_counter_;
+    };
+
+    // Exposed so it can be accessed by Simulator::{Read,Write}Ex*.
+    base::Mutex mutex;
+
+    void NotifyLoadExcl_Locked(uintptr_t addr, Processor* processor);
+    void NotifyStore_Locked(uintptr_t addr, Processor* processor);
+    bool NotifyStoreExcl_Locked(uintptr_t addr, Processor* processor);
+
+    // Called when the simulator is destroyed.
+    void RemoveProcessor(Processor* processor);
+
+   private:
+    bool IsProcessorInLinkedList_Locked(Processor* processor) const;
+    void PrependProcessor_Locked(Processor* processor);
+
+    Processor* head_;
+  };
+
+  LocalMonitor local_monitor_;
+  GlobalMonitor::Processor global_monitor_processor_;
+  static base::LazyInstance<GlobalMonitor>::type global_monitor_;
+
  private:
   void Init(FILE* stream);
 

test/cctest/BUILD.gn

@@ -224,6 +224,7 @@ v8_executable("cctest") {
       "test-javascript-arm64.cc",
       "test-js-arm64-variables.cc",
       "test-run-wasm-relocation-arm64.cc",
+      "test-simulator-arm64.cc",
       "test-utils-arm64.cc",
       "test-utils-arm64.h",
     ]

test/cctest/cctest.gyp

@@ -264,6 +264,7 @@
       'test-javascript-arm64.cc',
       'test-js-arm64-variables.cc',
       'test-run-wasm-relocation-arm64.cc',
+      'test-simulator-arm64.cc',
     ],
     'cctest_sources_s390': [  ### gcmole(arch:s390) ###
       'test-assembler-s390.cc',

test/cctest/test-simulator-arm.cc

@@ -67,10 +67,10 @@ struct MemoryAccess {
   MemoryAccess(Kind kind, Size size, size_t offset, int value = 0)
       : kind(kind), size(size), offset(offset), value(value) {}
 
-  Kind kind;
-  Size size;
-  size_t offset;
-  int value;
+  Kind kind = Kind::None;
+  Size size = Size::Byte;
+  size_t offset = 0;
+  int value = 0;
 };
 
 struct TestData {