[mips] Add bit left-rotation machine operator

Port c0eee179
https://crrev.com/c/2157648

Original Commit Message:

  ROL will be optional operator as arm, arm64 only have ROR.

  The reason for this CL is inefficient Wasm codegen for 64-bit
  left-rotation.

Change-Id: I014575d300a97c6fb7dc54d89328fd997d314d92
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2182219Reviewed-by: Tobias Tebbi <tebbi@chromium.org>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#67588}

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -714,6 +714,8 @@ void InstructionSelector::VisitWord32PairSar(Node* node) {
   VisitWord32PairShift(this, kMipsSarPair, node);
 }
 
+void InstructionSelector::VisitWord32Rol(Node* node) { UNREACHABLE(); }
+
 void InstructionSelector::VisitWord32Ror(Node* node) {
   VisitRRO(this, kMipsRor, node);
 }

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -852,6 +852,10 @@ void InstructionSelector::VisitWord64Sar(Node* node) {
   VisitRRO(this, kMips64Dsar, node);
 }
 
+void InstructionSelector::VisitWord32Rol(Node* node) { UNREACHABLE(); }
+
+void InstructionSelector::VisitWord64Rol(Node* node) { UNREACHABLE(); }
+
 void InstructionSelector::VisitWord32Ror(Node* node) {
   VisitRRO(this, kMips64Ror, node);
 }