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Commit 04527796 authored by Ng Zhi An's avatar Ng Zhi An Committed by V8 LUCI CQ
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[ia32][x64][cleanup] Clean up disassembly of fma instructions 

Declare more macro lists to split up W0 and W1, then disassemble using
the macro lists.

Change-Id: I4a73c24ea63c5a7b7489b81ee5ec7026c1765091
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3270598Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#77934}
parent 6faaf6e8
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Showing with 120 additions and 239 deletions
src/codegen/ia32/fma-instr.h
View file @ 04527796
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
#ifndef V8_CODEGEN_IA32_FMA_INSTR_H_ #ifndef V8_CODEGEN_IA32_FMA_INSTR_H_
#define V8_CODEGEN_IA32_FMA_INSTR_H_ #define V8_CODEGEN_IA32_FMA_INSTR_H_
#define FMA_INSTRUCTION_LIST(V) \ #define FMA_SD_INSTRUCTION_LIST(V) \
V(vfmadd132sd, L128, 66, 0F, 38, W1, 99) \ V(vfmadd132sd, L128, 66, 0F, 38, W1, 99) \
V(vfmadd213sd, L128, 66, 0F, 38, W1, a9) \ V(vfmadd213sd, L128, 66, 0F, 38, W1, a9) \
V(vfmadd231sd, L128, 66, 0F, 38, W1, b9) \ V(vfmadd231sd, L128, 66, 0F, 38, W1, b9) \
...@@ -17,25 +17,31 @@ ...@@ -17,25 +17,31 @@
V(vfnmadd231sd, L128, 66, 0F, 38, W1, bd) \ V(vfnmadd231sd, L128, 66, 0F, 38, W1, bd) \
V(vfnmsub132sd, L128, 66, 0F, 38, W1, 9f) \ V(vfnmsub132sd, L128, 66, 0F, 38, W1, 9f) \
V(vfnmsub213sd, L128, 66, 0F, 38, W1, af) \ V(vfnmsub213sd, L128, 66, 0F, 38, W1, af) \
V(vfnmsub231sd, L128, 66, 0F, 38, W1, bf) \ V(vfnmsub231sd, L128, 66, 0F, 38, W1, bf)
V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \ #define FMA_SS_INSTRUCTION_LIST(V) \
V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \ V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \ V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \
V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \ V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \
V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \ V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \
V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \ V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \
V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \ V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \
V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \ V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \
V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \ V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \
V(vfnmsub213ss, LIG, 66, 0F, 38, W0, af) \ V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \
V(vfnmsub231ss, LIG, 66, 0F, 38, W0, bf) \ V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \
V(vfnmsub213ss, LIG, 66, 0F, 38, W0, af) \
V(vfnmsub231ss, LIG, 66, 0F, 38, W0, bf)
#define FMA_PS_INSTRUCTION_LIST(V) \
V(vfmadd132ps, L128, 66, 0F, 38, W0, 98) \ V(vfmadd132ps, L128, 66, 0F, 38, W0, 98) \
V(vfmadd213ps, L128, 66, 0F, 38, W0, a8) \ V(vfmadd213ps, L128, 66, 0F, 38, W0, a8) \
V(vfmadd231ps, L128, 66, 0F, 38, W0, b8) \ V(vfmadd231ps, L128, 66, 0F, 38, W0, b8) \
V(vfnmadd132ps, L128, 66, 0F, 38, W0, 9c) \ V(vfnmadd132ps, L128, 66, 0F, 38, W0, 9c) \
V(vfnmadd213ps, L128, 66, 0F, 38, W0, ac) \ V(vfnmadd213ps, L128, 66, 0F, 38, W0, ac) \
V(vfnmadd231ps, L128, 66, 0F, 38, W0, bc) \ V(vfnmadd231ps, L128, 66, 0F, 38, W0, bc)
#define FMA_PD_INSTRUCTION_LIST(V) \
V(vfmadd132pd, L128, 66, 0F, 38, W1, 98) \ V(vfmadd132pd, L128, 66, 0F, 38, W1, 98) \
V(vfmadd213pd, L128, 66, 0F, 38, W1, a8) \ V(vfmadd213pd, L128, 66, 0F, 38, W1, a8) \
V(vfmadd231pd, L128, 66, 0F, 38, W1, b8) \ V(vfmadd231pd, L128, 66, 0F, 38, W1, b8) \
...@@ -43,4 +49,10 @@ ...@@ -43,4 +49,10 @@
V(vfnmadd213pd, L128, 66, 0F, 38, W1, ac) \ V(vfnmadd213pd, L128, 66, 0F, 38, W1, ac) \
V(vfnmadd231pd, L128, 66, 0F, 38, W1, bc) V(vfnmadd231pd, L128, 66, 0F, 38, W1, bc)
#define FMA_INSTRUCTION_LIST(V) \
FMA_SD_INSTRUCTION_LIST(V) \
FMA_SS_INSTRUCTION_LIST(V) \
FMA_PS_INSTRUCTION_LIST(V) \
FMA_PD_INSTRUCTION_LIST(V)
#endif // V8_CODEGEN_IA32_FMA_INSTR_H_ #endif // V8_CODEGEN_IA32_FMA_INSTR_H_
src/codegen/x64/fma-instr.h
View file @ 04527796
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
#ifndef V8_CODEGEN_X64_FMA_INSTR_H_ #ifndef V8_CODEGEN_X64_FMA_INSTR_H_
#define V8_CODEGEN_X64_FMA_INSTR_H_ #define V8_CODEGEN_X64_FMA_INSTR_H_
#define FMA_INSTRUCTION_LIST(V) \ #define FMA_SD_INSTRUCTION_LIST(V) \
V(vfmadd132sd, L128, 66, 0F, 38, W1, 99) \ V(vfmadd132sd, L128, 66, 0F, 38, W1, 99) \
V(vfmadd213sd, L128, 66, 0F, 38, W1, a9) \ V(vfmadd213sd, L128, 66, 0F, 38, W1, a9) \
V(vfmadd231sd, L128, 66, 0F, 38, W1, b9) \ V(vfmadd231sd, L128, 66, 0F, 38, W1, b9) \
...@@ -17,25 +17,31 @@ ...@@ -17,25 +17,31 @@
V(vfnmadd231sd, L128, 66, 0F, 38, W1, bd) \ V(vfnmadd231sd, L128, 66, 0F, 38, W1, bd) \
V(vfnmsub132sd, L128, 66, 0F, 38, W1, 9f) \ V(vfnmsub132sd, L128, 66, 0F, 38, W1, 9f) \
V(vfnmsub213sd, L128, 66, 0F, 38, W1, af) \ V(vfnmsub213sd, L128, 66, 0F, 38, W1, af) \
V(vfnmsub231sd, L128, 66, 0F, 38, W1, bf) \ V(vfnmsub231sd, L128, 66, 0F, 38, W1, bf)
V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \ #define FMA_SS_INSTRUCTION_LIST(V) \
V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \ V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \ V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \
V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \ V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \
V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \ V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \
V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \ V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \
V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \ V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \
V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \ V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \
V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \ V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \
V(vfnmsub213ss, LIG, 66, 0F, 38, W0, af) \ V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \
V(vfnmsub231ss, LIG, 66, 0F, 38, W0, bf) \ V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \
V(vfnmsub213ss, LIG, 66, 0F, 38, W0, af) \
V(vfnmsub231ss, LIG, 66, 0F, 38, W0, bf)
#define FMA_PS_INSTRUCTION_LIST(V) \
V(vfmadd132ps, L128, 66, 0F, 38, W0, 98) \ V(vfmadd132ps, L128, 66, 0F, 38, W0, 98) \
V(vfmadd213ps, L128, 66, 0F, 38, W0, a8) \ V(vfmadd213ps, L128, 66, 0F, 38, W0, a8) \
V(vfmadd231ps, L128, 66, 0F, 38, W0, b8) \ V(vfmadd231ps, L128, 66, 0F, 38, W0, b8) \
V(vfnmadd132ps, L128, 66, 0F, 38, W0, 9c) \ V(vfnmadd132ps, L128, 66, 0F, 38, W0, 9c) \
V(vfnmadd213ps, L128, 66, 0F, 38, W0, ac) \ V(vfnmadd213ps, L128, 66, 0F, 38, W0, ac) \
V(vfnmadd231ps, L128, 66, 0F, 38, W0, bc) \ V(vfnmadd231ps, L128, 66, 0F, 38, W0, bc)
#define FMA_PD_INSTRUCTION_LIST(V) \
V(vfmadd132pd, L128, 66, 0F, 38, W1, 98) \ V(vfmadd132pd, L128, 66, 0F, 38, W1, 98) \
V(vfmadd213pd, L128, 66, 0F, 38, W1, a8) \ V(vfmadd213pd, L128, 66, 0F, 38, W1, a8) \
V(vfmadd231pd, L128, 66, 0F, 38, W1, b8) \ V(vfmadd231pd, L128, 66, 0F, 38, W1, b8) \
...@@ -43,4 +49,10 @@ ...@@ -43,4 +49,10 @@
V(vfnmadd213pd, L128, 66, 0F, 38, W1, ac) \ V(vfnmadd213pd, L128, 66, 0F, 38, W1, ac) \
V(vfnmadd231pd, L128, 66, 0F, 38, W1, bc) V(vfnmadd231pd, L128, 66, 0F, 38, W1, bc)
#define FMA_INSTRUCTION_LIST(V) \
FMA_SD_INSTRUCTION_LIST(V) \
FMA_SS_INSTRUCTION_LIST(V) \
FMA_PS_INSTRUCTION_LIST(V) \
FMA_PD_INSTRUCTION_LIST(V)
#endif // V8_CODEGEN_X64_FMA_INSTR_H_ #endif // V8_CODEGEN_X64_FMA_INSTR_H_
src/diagnostics/ia32/disasm-ia32.cc
View file @ 04527796
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include "src/base/compiler-specific.h" #include "src/base/compiler-specific.h"
#include "src/base/strings.h" #include "src/base/strings.h"
#include "src/codegen/ia32/fma-instr.h"
#include "src/codegen/ia32/sse-instr.h" #include "src/codegen/ia32/sse-instr.h"
#include "src/diagnostics/disasm.h" #include "src/diagnostics/disasm.h"
...@@ -702,66 +703,6 @@ int DisassemblerIA32::AVXInstruction(byte* data) { ...@@ -702,66 +703,6 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv)); NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current); current += PrintRightXMMOperand(current);
break; break;
case 0x99:
AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xA9:
AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xB9:
AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x9B:
AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAB:
AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBB:
AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x9D:
AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAD:
AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBD:
AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x9F:
AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAF:
AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBF:
AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xF7: case 0xF7:
AppendToBuffer("shlx %s,", NameOfCPURegister(regop)); AppendToBuffer("shlx %s,", NameOfCPURegister(regop));
current += PrintRightOperand(current); current += PrintRightOperand(current);
...@@ -799,8 +740,35 @@ int DisassemblerIA32::AVXInstruction(byte* data) { ...@@ -799,8 +740,35 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
AVX2_BROADCAST_LIST(DISASSEMBLE_AVX2_BROADCAST) AVX2_BROADCAST_LIST(DISASSEMBLE_AVX2_BROADCAST)
#undef DISASSEMBLE_AVX2_BROADCAST #undef DISASSEMBLE_AVX2_BROADCAST
default: default: {
UnimplementedInstruction(); #define DECLARE_FMA_DISASM(instruction, _1, _2, _3, _4, _5, code) \
case 0x##code: { \
AppendToBuffer(#instruction " %s,%s,", NameOfXMMRegister(regop), \
NameOfXMMRegister(vvvv)); \
current += PrintRightXMMOperand(current); \
break; \
}
// Handle all the fma instructions here in the default branch since they
// have the same opcodes but differ by rex_w.
if (vex_w()) {
switch (opcode) {
FMA_SS_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
FMA_PS_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
default: {
UnimplementedInstruction();
}
}
} else {
switch (opcode) {
FMA_SD_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
FMA_PD_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
default: {
UnimplementedInstruction();
}
}
}
#undef DECLARE_FMA_DISASM
}
} }
} else if (vex_66() && vex_0f3a()) { } else if (vex_66() && vex_0f3a()) {
int mod, regop, rm, vvvv = vex_vreg(); int mod, regop, rm, vvvv = vex_vreg();
......
src/diagnostics/x64/disasm-x64.cc
View file @ 04527796
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include "src/base/memory.h" #include "src/base/memory.h"
#include "src/base/strings.h" #include "src/base/strings.h"
#include "src/base/v8-fallthrough.h" #include "src/base/v8-fallthrough.h"
#include "src/codegen/x64/fma-instr.h"
#include "src/codegen/x64/register-x64.h" #include "src/codegen/x64/register-x64.h"
#include "src/codegen/x64/sse-instr.h" #include "src/codegen/x64/sse-instr.h"
#include "src/common/globals.h" #include "src/common/globals.h"
...@@ -893,96 +894,6 @@ int DisassemblerX64::AVXInstruction(byte* data) { ...@@ -893,96 +894,6 @@ int DisassemblerX64::AVXInstruction(byte* data) {
AppendToBuffer("vbroadcastss %s,", NameOfAVXRegister(regop)); AppendToBuffer("vbroadcastss %s,", NameOfAVXRegister(regop));
current += PrintRightXMMOperand(current); current += PrintRightXMMOperand(current);
break; break;
case 0x98:
AppendToBuffer("vfmadd132p%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x99:
AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xA8:
AppendToBuffer("vfmadd213p%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xA9:
AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xB8:
AppendToBuffer("vfmadd231p%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xB9:
AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0x9B:
AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0x9C:
AppendToBuffer("vfnmadd132p%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAB:
AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xAC:
AppendToBuffer("vfnmadd213p%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBB:
AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xBC:
AppendToBuffer("vfnmadd231p%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0x9D:
AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xAD:
AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xBD:
AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0x9F:
AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xAF:
AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xBF:
AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
NameOfAVXRegister(regop), NameOfAVXRegister(vvvv));
current += PrintRightAVXOperand(current);
break;
case 0xF7: case 0xF7:
AppendToBuffer("shlx%c %s,", operand_size_code(), AppendToBuffer("shlx%c %s,", operand_size_code(),
NameOfCPURegister(regop)); NameOfCPURegister(regop));
...@@ -1022,8 +933,35 @@ int DisassemblerX64::AVXInstruction(byte* data) { ...@@ -1022,8 +933,35 @@ int DisassemblerX64::AVXInstruction(byte* data) {
AVX2_BROADCAST_LIST(DISASSEMBLE_AVX2_BROADCAST) AVX2_BROADCAST_LIST(DISASSEMBLE_AVX2_BROADCAST)
#undef DISASSEMBLE_AVX2_BROADCAST #undef DISASSEMBLE_AVX2_BROADCAST
default: default: {
UnimplementedInstruction(); #define DECLARE_FMA_DISASM(instruction, _1, _2, _3, _4, _5, code) \
case 0x##code: { \
AppendToBuffer(#instruction " %s,%s,", NameOfAVXRegister(regop), \
NameOfAVXRegister(vvvv)); \
current += PrintRightAVXOperand(current); \
break; \
}
// Handle all the fma instructions here in the default branch since they
// have the same opcodes but differ by rex_w.
if (rex_w()) {
switch (opcode) {
FMA_SS_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
FMA_PS_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
default: {
UnimplementedInstruction();
}
}
} else {
switch (opcode) {
FMA_SD_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
FMA_PD_INSTRUCTION_LIST(DECLARE_FMA_DISASM)
default: {
UnimplementedInstruction();
}
}
}
#undef DECLARE_FMA_DISASM
}
} }
} else if (vex_66() && vex_0f3a()) { } else if (vex_66() && vex_0f3a()) {
int mod, regop, rm, vvvv = vex_vreg(); int mod, regop, rm, vvvv = vex_vreg();
......
test/cctest/test-disasm-ia32.cc
View file @ 04527796
...@@ -873,61 +873,12 @@ TEST(DisasmIa320) { ...@@ -873,61 +873,12 @@ TEST(DisasmIa320) {
{ {
if (CpuFeatures::IsSupported(FMA3)) { if (CpuFeatures::IsSupported(FMA3)) {
CpuFeatureScope scope(&assm, FMA3); CpuFeatureScope scope(&assm, FMA3);
__ vfmadd132sd(xmm0, xmm1, xmm2); #define EMIT_FMA(instr, notUsed1, notUsed2, notUsed3, notUsed4, notUsed5, \
__ vfmadd132sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000)); notUsed6) \
__ vfmadd213sd(xmm0, xmm1, xmm2); __ instr(xmm2, xmm1, xmm0); \
__ vfmadd213sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000)); __ instr(xmm2, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmadd231sd(xmm0, xmm1, xmm2); FMA_INSTRUCTION_LIST(EMIT_FMA)
__ vfmadd231sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000)); #undef EMIT_FMA
__ vfmsub132sd(xmm0, xmm1, xmm2);
__ vfmsub132sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmsub213sd(xmm0, xmm1, xmm2);
__ vfmsub213sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmsub231sd(xmm0, xmm1, xmm2);
__ vfmsub231sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmadd132sd(xmm0, xmm1, xmm2);
__ vfnmadd132sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmadd213sd(xmm0, xmm1, xmm2);
__ vfnmadd213sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmadd231sd(xmm0, xmm1, xmm2);
__ vfnmadd231sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmsub132sd(xmm0, xmm1, xmm2);
__ vfnmsub132sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmsub213sd(xmm0, xmm1, xmm2);
__ vfnmsub213sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmsub231sd(xmm0, xmm1, xmm2);
__ vfnmsub231sd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmadd132ss(xmm0, xmm1, xmm2);
__ vfmadd132ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmadd213ss(xmm0, xmm1, xmm2);
__ vfmadd213ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmadd231ss(xmm0, xmm1, xmm2);
__ vfmadd231ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmsub132ss(xmm0, xmm1, xmm2);
__ vfmsub132ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmsub213ss(xmm0, xmm1, xmm2);
__ vfmsub213ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfmsub231ss(xmm0, xmm1, xmm2);
__ vfmsub231ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmadd132ss(xmm0, xmm1, xmm2);
__ vfnmadd132ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmadd213ss(xmm0, xmm1, xmm2);
__ vfnmadd213ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmadd231ss(xmm0, xmm1, xmm2);
__ vfnmadd231ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmsub132ss(xmm0, xmm1, xmm2);
__ vfnmsub132ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmsub213ss(xmm0, xmm1, xmm2);
__ vfnmsub213ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vfnmsub231ss(xmm0, xmm1, xmm2);
__ vfnmsub231ss(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
} }
} }
......
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