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Commit 0237747a authored by Clemens Hammacher's avatar Clemens Hammacher Committed by Commit Bot
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[Assembler][x64] Pass Operand by value 

The Operand class is small enough to be efficiently passed by value.
This saves binary size and performance because the Operand does not need
to be emitted to the caller's frame and loaded in the callee.
Binary saving is 30kB in release mode on x64.

R=mstarzinger@chromium.org

Bug: v8:7310
Change-Id: Ibad9d438ace23cfe8e4641bd48063ab7035656f4
Reviewed-on: https://chromium-review.googlesource.com/934137
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#51524}
parent bdec7137
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Showing with 599 additions and 810 deletions
src/x64/assembler-x64-inl.h
View file @ 0237747a
......@@ -92,13 +92,11 @@ void Assembler::emit_rex_64(Register reg, XMMRegister rm_reg) {
emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3);
}
void Assembler::emit_rex_64(Register reg, const Operand& op) {
void Assembler::emit_rex_64(Register reg, Operand op) {
emit(0x48 | reg.high_bit() << 2 | op.rex_);
}
void Assembler::emit_rex_64(XMMRegister reg, const Operand& op) {
void Assembler::emit_rex_64(XMMRegister reg, Operand op) {
emit(0x48 | (reg.code() & 0x8) >> 1 | op.rex_);
}
......@@ -108,18 +106,13 @@ void Assembler::emit_rex_64(Register rm_reg) {
emit(0x48 | rm_reg.high_bit());
}
void Assembler::emit_rex_64(const Operand& op) {
emit(0x48 | op.rex_);
}
void Assembler::emit_rex_64(Operand op) { emit(0x48 | op.rex_); }
void Assembler::emit_rex_32(Register reg, Register rm_reg) {
emit(0x40 | reg.high_bit() << 2 | rm_reg.high_bit());
}
void Assembler::emit_rex_32(Register reg, const Operand& op) {
void Assembler::emit_rex_32(Register reg, Operand op) {
emit(0x40 | reg.high_bit() << 2 | op.rex_);
}
......@@ -128,25 +121,19 @@ void Assembler::emit_rex_32(Register rm_reg) {
emit(0x40 | rm_reg.high_bit());
}
void Assembler::emit_rex_32(const Operand& op) {
emit(0x40 | op.rex_);
}
void Assembler::emit_rex_32(Operand op) { emit(0x40 | op.rex_); }
void Assembler::emit_optional_rex_32(Register reg, Register rm_reg) {
byte rex_bits = reg.high_bit() << 2 | rm_reg.high_bit();
if (rex_bits != 0) emit(0x40 | rex_bits);
}
void Assembler::emit_optional_rex_32(Register reg, const Operand& op) {
void Assembler::emit_optional_rex_32(Register reg, Operand op) {
byte rex_bits = reg.high_bit() << 2 | op.rex_;
if (rex_bits != 0) emit(0x40 | rex_bits);
}
void Assembler::emit_optional_rex_32(XMMRegister reg, const Operand& op) {
void Assembler::emit_optional_rex_32(XMMRegister reg, Operand op) {
byte rex_bits = (reg.code() & 0x8) >> 1 | op.rex_;
if (rex_bits != 0) emit(0x40 | rex_bits);
}
......@@ -178,7 +165,7 @@ void Assembler::emit_optional_rex_32(XMMRegister rm_reg) {
if (rm_reg.high_bit()) emit(0x41);
}
void Assembler::emit_optional_rex_32(const Operand& op) {
void Assembler::emit_optional_rex_32(Operand op) {
if (op.rex_ != 0) emit(0x40 | op.rex_);
}
......@@ -192,8 +179,7 @@ void Assembler::emit_vex3_byte1(XMMRegister reg, XMMRegister rm,
// byte 1 of 3-byte VEX
void Assembler::emit_vex3_byte1(XMMRegister reg, const Operand& rm,
LeadingOpcode m) {
void Assembler::emit_vex3_byte1(XMMRegister reg, Operand rm, LeadingOpcode m) {
byte rxb = ~((reg.high_bit() << 2) | rm.rex_) << 5;
emit(rxb | m);
}
......@@ -237,10 +223,9 @@ void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm,
emit_vex_prefix(ireg, ivreg, irm, l, pp, mm, w);
}
void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg,
const Operand& rm, VectorLength l,
SIMDPrefix pp, LeadingOpcode mm, VexW w) {
void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, Operand rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode mm,
VexW w) {
if (rm.rex_ || mm != k0F || w != kW0) {
emit_vex3_byte0();
emit_vex3_byte1(reg, rm, mm);
......@@ -251,8 +236,7 @@ void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg,
}
}
void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm,
void Assembler::emit_vex_prefix(Register reg, Register vreg, Operand rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode mm,
VexW w) {
XMMRegister ireg = XMMRegister::from_code(reg.code());
......
src/x64/assembler-x64.cc
View file @ 0237747a
......@@ -214,8 +214,7 @@ Operand::Operand(Label* label, int addend) : rex_(0), len_(1), addend_(addend) {
set_disp64(reinterpret_cast<intptr_t>(label));
}
Operand::Operand(const Operand& operand, int32_t offset) {
Operand::Operand(Operand operand, int32_t offset) {
DCHECK_GE(operand.len_, 1);
// Operand encodes REX ModR/M [SIB] [Disp].
byte modrm = operand.buf_[0];
......@@ -527,8 +526,7 @@ void Assembler::GrowBuffer() {
DCHECK(!buffer_overflow());
}
void Assembler::emit_operand(int code, const Operand& adr) {
void Assembler::emit_operand(int code, Operand adr) {
DCHECK(is_uint3(code));
const unsigned length = adr.len_;
DCHECK_GT(length, 0);
......@@ -563,10 +561,7 @@ void Assembler::emit_operand(int code, const Operand& adr) {
// Assembler Instruction implementations.
void Assembler::arithmetic_op(byte opcode,
Register reg,
const Operand& op,
int size) {
void Assembler::arithmetic_op(byte opcode, Register reg, Operand op, int size) {
EnsureSpace ensure_space(this);
emit_rex(reg, op, size);
emit(opcode);
......@@ -610,10 +605,7 @@ void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_reg) {
}
}
void Assembler::arithmetic_op_16(byte opcode,
Register reg,
const Operand& rm_reg) {
void Assembler::arithmetic_op_16(byte opcode, Register reg, Operand rm_reg) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(reg, rm_reg);
......@@ -621,8 +613,7 @@ void Assembler::arithmetic_op_16(byte opcode,
emit_operand(reg, rm_reg);
}
void Assembler::arithmetic_op_8(byte opcode, Register reg, const Operand& op) {
void Assembler::arithmetic_op_8(byte opcode, Register reg, Operand op) {
EnsureSpace ensure_space(this);
if (!reg.is_byte_register()) {
emit_rex_32(reg, op);
......@@ -676,10 +667,8 @@ void Assembler::immediate_arithmetic_op(byte subcode,
}
}
void Assembler::immediate_arithmetic_op(byte subcode,
const Operand& dst,
Immediate src,
int size) {
void Assembler::immediate_arithmetic_op(byte subcode, Operand dst,
Immediate src, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, size);
if (is_int8(src.value_) && RelocInfo::IsNone(src.rmode_)) {
......@@ -714,9 +703,7 @@ void Assembler::immediate_arithmetic_op_16(byte subcode,
}
}
void Assembler::immediate_arithmetic_op_16(byte subcode,
const Operand& dst,
void Assembler::immediate_arithmetic_op_16(byte subcode, Operand dst,
Immediate src) {
EnsureSpace ensure_space(this);
emit(0x66); // Operand size override prefix.
......@@ -732,9 +719,7 @@ void Assembler::immediate_arithmetic_op_16(byte subcode,
}
}
void Assembler::immediate_arithmetic_op_8(byte subcode,
const Operand& dst,
void Assembler::immediate_arithmetic_op_8(byte subcode, Operand dst,
Immediate src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst);
......@@ -813,8 +798,7 @@ void Assembler::shift(Operand dst, int subcode, int size) {
emit_operand(subcode, dst);
}
void Assembler::bt(const Operand& dst, Register src) {
void Assembler::bt(Operand dst, Register src) {
EnsureSpace ensure_space(this);
emit_rex_64(src, dst);
emit(0x0F);
......@@ -822,8 +806,7 @@ void Assembler::bt(const Operand& dst, Register src) {
emit_operand(src, dst);
}
void Assembler::bts(const Operand& dst, Register src) {
void Assembler::bts(Operand dst, Register src) {
EnsureSpace ensure_space(this);
emit_rex_64(src, dst);
emit(0x0F);
......@@ -840,8 +823,7 @@ void Assembler::bsrl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::bsrl(Register dst, const Operand& src) {
void Assembler::bsrl(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -858,8 +840,7 @@ void Assembler::bsrq(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::bsrq(Register dst, const Operand& src) {
void Assembler::bsrq(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_rex_64(dst, src);
emit(0x0F);
......@@ -876,8 +857,7 @@ void Assembler::bsfl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::bsfl(Register dst, const Operand& src) {
void Assembler::bsfl(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -894,8 +874,7 @@ void Assembler::bsfq(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::bsfq(Register dst, const Operand& src) {
void Assembler::bsfq(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_rex_64(dst, src);
emit(0x0F);
......@@ -912,7 +891,7 @@ void Assembler::pshufw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
emit(shuffle);
}
void Assembler::pshufw(XMMRegister dst, const Operand& src, uint8_t shuffle) {
void Assembler::pshufw(XMMRegister dst, Operand src, uint8_t shuffle) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -990,8 +969,7 @@ void Assembler::call(Register adr) {
emit_modrm(0x2, adr);
}
void Assembler::call(const Operand& op) {
void Assembler::call(Operand op) {
EnsureSpace ensure_space(this);
// Opcode: FF /2 m64.
emit_optional_rex_32(op);
......@@ -1049,8 +1027,7 @@ void Assembler::cmovq(Condition cc, Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::cmovq(Condition cc, Register dst, const Operand& src) {
void Assembler::cmovq(Condition cc, Register dst, Operand src) {
if (cc == always) {
movq(dst, src);
} else if (cc == never) {
......@@ -1081,8 +1058,7 @@ void Assembler::cmovl(Condition cc, Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
void Assembler::cmovl(Condition cc, Register dst, Operand src) {
if (cc == always) {
movl(dst, src);
} else if (cc == never) {
......@@ -1110,7 +1086,7 @@ void Assembler::lock() {
emit(0xF0);
}
void Assembler::cmpxchgb(const Operand& dst, Register src) {
void Assembler::cmpxchgb(Operand dst, Register src) {
EnsureSpace ensure_space(this);
if (!src.is_byte_register()) {
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
......@@ -1123,7 +1099,7 @@ void Assembler::cmpxchgb(const Operand& dst, Register src) {
emit_operand(src, dst);
}
void Assembler::cmpxchgw(const Operand& dst, Register src) {
void Assembler::cmpxchgw(Operand dst, Register src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(src, dst);
......@@ -1132,7 +1108,7 @@ void Assembler::cmpxchgw(const Operand& dst, Register src) {
emit_operand(src, dst);
}
void Assembler::emit_cmpxchg(const Operand& dst, Register src, int size) {
void Assembler::emit_cmpxchg(Operand dst, Register src, int size) {
EnsureSpace ensure_space(this);
emit_rex(src, dst, size);
emit(0x0F);
......@@ -1168,8 +1144,7 @@ void Assembler::emit_dec(Register dst, int size) {
emit_modrm(0x1, dst);
}
void Assembler::emit_dec(const Operand& dst, int size) {
void Assembler::emit_dec(Operand dst, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, size);
emit(0xFF);
......@@ -1187,8 +1162,7 @@ void Assembler::decb(Register dst) {
emit_modrm(0x1, dst);
}
void Assembler::decb(const Operand& dst) {
void Assembler::decb(Operand dst) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst);
emit(0xFE);
......@@ -1233,8 +1207,7 @@ void Assembler::emit_imul(Register src, int size) {
emit_modrm(0x5, src);
}
void Assembler::emit_imul(const Operand& src, int size) {
void Assembler::emit_imul(Operand src, int size) {
EnsureSpace ensure_space(this);
emit_rex(src, size);
emit(0xF7);
......@@ -1250,8 +1223,7 @@ void Assembler::emit_imul(Register dst, Register src, int size) {
emit_modrm(dst, src);
}
void Assembler::emit_imul(Register dst, const Operand& src, int size) {
void Assembler::emit_imul(Register dst, Operand src, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, src, size);
emit(0x0F);
......@@ -1274,9 +1246,7 @@ void Assembler::emit_imul(Register dst, Register src, Immediate imm, int size) {
}
}
void Assembler::emit_imul(Register dst, const Operand& src, Immediate imm,
int size) {
void Assembler::emit_imul(Register dst, Operand src, Immediate imm, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, src, size);
if (is_int8(imm.value_)) {
......@@ -1298,8 +1268,7 @@ void Assembler::emit_inc(Register dst, int size) {
emit_modrm(0x0, dst);
}
void Assembler::emit_inc(const Operand& dst, int size) {
void Assembler::emit_inc(Operand dst, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, size);
emit(0xFF);
......@@ -1483,8 +1452,7 @@ void Assembler::jmp(Register target) {
emit_modrm(0x4, target);
}
void Assembler::jmp(const Operand& src) {
void Assembler::jmp(Operand src) {
EnsureSpace ensure_space(this);
// Opcode FF/4 m64.
emit_optional_rex_32(src);
......@@ -1492,8 +1460,7 @@ void Assembler::jmp(const Operand& src) {
emit_operand(0x4, src);
}
void Assembler::emit_lea(Register dst, const Operand& src, int size) {
void Assembler::emit_lea(Register dst, Operand src, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, src, size);
emit(0x8D);
......@@ -1529,8 +1496,7 @@ void Assembler::leave() {
emit(0xC9);
}
void Assembler::movb(Register dst, const Operand& src) {
void Assembler::movb(Register dst, Operand src) {
EnsureSpace ensure_space(this);
if (!dst.is_byte_register()) {
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
......@@ -1553,8 +1519,7 @@ void Assembler::movb(Register dst, Immediate imm) {
emit(imm.value_);
}
void Assembler::movb(const Operand& dst, Register src) {
void Assembler::movb(Operand dst, Register src) {
EnsureSpace ensure_space(this);
if (!src.is_byte_register()) {
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
......@@ -1566,8 +1531,7 @@ void Assembler::movb(const Operand& dst, Register src) {
emit_operand(src, dst);
}
void Assembler::movb(const Operand& dst, Immediate imm) {
void Assembler::movb(Operand dst, Immediate imm) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst);
emit(0xC6);
......@@ -1575,8 +1539,7 @@ void Assembler::movb(const Operand& dst, Immediate imm) {
emit(static_cast<byte>(imm.value_));
}
void Assembler::movw(Register dst, const Operand& src) {
void Assembler::movw(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
......@@ -1584,8 +1547,7 @@ void Assembler::movw(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::movw(const Operand& dst, Register src) {
void Assembler::movw(Operand dst, Register src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(src, dst);
......@@ -1593,8 +1555,7 @@ void Assembler::movw(const Operand& dst, Register src) {
emit_operand(src, dst);
}
void Assembler::movw(const Operand& dst, Immediate imm) {
void Assembler::movw(Operand dst, Immediate imm) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst);
......@@ -1604,8 +1565,7 @@ void Assembler::movw(const Operand& dst, Immediate imm) {
emit(static_cast<byte>(imm.value_ >> 8));
}
void Assembler::emit_mov(Register dst, const Operand& src, int size) {
void Assembler::emit_mov(Register dst, Operand src, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, src, size);
emit(0x8B);
......@@ -1626,8 +1586,7 @@ void Assembler::emit_mov(Register dst, Register src, int size) {
}
}
void Assembler::emit_mov(const Operand& dst, Register src, int size) {
void Assembler::emit_mov(Operand dst, Register src, int size) {
EnsureSpace ensure_space(this);
emit_rex(src, dst, size);
emit(0x89);
......@@ -1648,8 +1607,7 @@ void Assembler::emit_mov(Register dst, Immediate value, int size) {
emit(value);
}
void Assembler::emit_mov(const Operand& dst, Immediate value, int size) {
void Assembler::emit_mov(Operand dst, Immediate value, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, size);
emit(0xC7);
......@@ -1689,7 +1647,7 @@ void Assembler::movq(Register dst, uint64_t value, RelocInfo::Mode rmode) {
// Loads the ip-relative location of the src label into the target location
// (as a 32-bit offset sign extended to 64-bit).
void Assembler::movl(const Operand& dst, Label* src) {
void Assembler::movl(Operand dst, Label* src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst);
emit(0xC7);
......@@ -1723,8 +1681,7 @@ void Assembler::movsxbl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::movsxbl(Register dst, const Operand& src) {
void Assembler::movsxbl(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -1732,8 +1689,7 @@ void Assembler::movsxbl(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::movsxbq(Register dst, const Operand& src) {
void Assembler::movsxbq(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_rex_64(dst, src);
emit(0x0F);
......@@ -1757,8 +1713,7 @@ void Assembler::movsxwl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::movsxwl(Register dst, const Operand& src) {
void Assembler::movsxwl(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -1766,8 +1721,7 @@ void Assembler::movsxwl(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::movsxwq(Register dst, const Operand& src) {
void Assembler::movsxwq(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_rex_64(dst, src);
emit(0x0F);
......@@ -1790,16 +1744,14 @@ void Assembler::movsxlq(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::movsxlq(Register dst, const Operand& src) {
void Assembler::movsxlq(Register dst, Operand src) {
EnsureSpace ensure_space(this);
emit_rex_64(dst, src);
emit(0x63);
emit_operand(dst, src);
}
void Assembler::emit_movzxb(Register dst, const Operand& src, int size) {
void Assembler::emit_movzxb(Register dst, Operand src, int size) {
EnsureSpace ensure_space(this);
// 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
// there is no need to make this a 64 bit operation.
......@@ -1825,8 +1777,7 @@ void Assembler::emit_movzxb(Register dst, Register src, int size) {
emit_modrm(dst, src);
}
void Assembler::emit_movzxw(Register dst, const Operand& src, int size) {
void Assembler::emit_movzxw(Register dst, Operand src, int size) {
EnsureSpace ensure_space(this);
// 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
// there is no need to make this a 64 bit operation.
......@@ -1878,8 +1829,7 @@ void Assembler::mull(Register src) {
emit_modrm(0x4, src);
}
void Assembler::mull(const Operand& src) {
void Assembler::mull(Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(src);
emit(0xF7);
......@@ -1902,8 +1852,7 @@ void Assembler::emit_neg(Register dst, int size) {
emit_modrm(0x3, dst);
}
void Assembler::emit_neg(const Operand& dst, int size) {
void Assembler::emit_neg(Operand dst, int size) {
EnsureSpace ensure_space(this);
emit_rex_64(dst);
emit(0xF7);
......@@ -1924,8 +1873,7 @@ void Assembler::emit_not(Register dst, int size) {
emit_modrm(0x2, dst);
}
void Assembler::emit_not(const Operand& dst, int size) {
void Assembler::emit_not(Operand dst, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, size);
emit(0xF7);
......@@ -2021,8 +1969,7 @@ void Assembler::popq(Register dst) {
emit(0x58 | dst.low_bits());
}
void Assembler::popq(const Operand& dst) {
void Assembler::popq(Operand dst) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst);
emit(0x8F);
......@@ -2042,8 +1989,7 @@ void Assembler::pushq(Register src) {
emit(0x50 | src.low_bits());
}
void Assembler::pushq(const Operand& src) {
void Assembler::pushq(Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(src);
emit(0xFF);
......@@ -2130,7 +2076,7 @@ void Assembler::shrd(Register dst, Register src) {
emit_modrm(src, dst);
}
void Assembler::xchgb(Register reg, const Operand& op) {
void Assembler::xchgb(Register reg, Operand op) {
EnsureSpace ensure_space(this);
if (!reg.is_byte_register()) {
// Register is not one of al, bl, cl, dl. Its encoding needs REX.
......@@ -2142,7 +2088,7 @@ void Assembler::xchgb(Register reg, const Operand& op) {
emit_operand(reg, op);
}
void Assembler::xchgw(Register reg, const Operand& op) {
void Assembler::xchgw(Register reg, Operand op) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(reg, op);
......@@ -2167,8 +2113,7 @@ void Assembler::emit_xchg(Register dst, Register src, int size) {
}
}
void Assembler::emit_xchg(Register dst, const Operand& src, int size) {
void Assembler::emit_xchg(Register dst, Operand src, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, src, size);
emit(0x87);
......@@ -2215,13 +2160,12 @@ void Assembler::testb(Register reg, Immediate mask) {
emit_test(reg, mask, sizeof(int8_t));
}
void Assembler::testb(const Operand& op, Immediate mask) {
void Assembler::testb(Operand op, Immediate mask) {
DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
emit_test(op, mask, sizeof(int8_t));
}
void Assembler::testb(const Operand& op, Register reg) {
void Assembler::testb(Operand op, Register reg) {
emit_test(op, reg, sizeof(int8_t));
}
......@@ -2233,11 +2177,11 @@ void Assembler::testw(Register reg, Immediate mask) {
emit_test(reg, mask, sizeof(int16_t));
}
void Assembler::testw(const Operand& op, Immediate mask) {
void Assembler::testw(Operand op, Immediate mask) {
emit_test(op, mask, sizeof(int16_t));
}
void Assembler::testw(const Operand& op, Register reg) {
void Assembler::testw(Operand op, Register reg) {
emit_test(op, reg, sizeof(int16_t));
}
......@@ -2296,7 +2240,7 @@ void Assembler::emit_test(Register reg, Immediate mask, int size) {
}
}
void Assembler::emit_test(const Operand& op, Immediate mask, int size) {
void Assembler::emit_test(Operand op, Immediate mask, int size) {
if (is_uint8(mask.value_)) {
size = sizeof(int8_t);
} else if (is_uint16(mask.value_)) {
......@@ -2324,7 +2268,7 @@ void Assembler::emit_test(const Operand& op, Immediate mask, int size) {
}
}
void Assembler::emit_test(const Operand& op, Register reg, int size) {
void Assembler::emit_test(Operand op, Register reg, int size) {
EnsureSpace ensure_space(this);
if (size == sizeof(int16_t)) {
emit(0x66);
......@@ -2383,32 +2327,28 @@ void Assembler::fldln2() {
emit(0xED);
}
void Assembler::fld_s(const Operand& adr) {
void Assembler::fld_s(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xD9);
emit_operand(0, adr);
}
void Assembler::fld_d(const Operand& adr) {
void Assembler::fld_d(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDD);
emit_operand(0, adr);
}
void Assembler::fstp_s(const Operand& adr) {
void Assembler::fstp_s(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xD9);
emit_operand(3, adr);
}
void Assembler::fstp_d(const Operand& adr) {
void Assembler::fstp_d(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDD);
......@@ -2422,32 +2362,28 @@ void Assembler::fstp(int index) {
emit_farith(0xDD, 0xD8, index);
}
void Assembler::fild_s(const Operand& adr) {
void Assembler::fild_s(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDB);
emit_operand(0, adr);
}
void Assembler::fild_d(const Operand& adr) {
void Assembler::fild_d(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDF);
emit_operand(5, adr);
}
void Assembler::fistp_s(const Operand& adr) {
void Assembler::fistp_s(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDB);
emit_operand(3, adr);
}
void Assembler::fisttp_s(const Operand& adr) {
void Assembler::fisttp_s(Operand adr) {
DCHECK(IsEnabled(SSE3));
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
......@@ -2455,8 +2391,7 @@ void Assembler::fisttp_s(const Operand& adr) {
emit_operand(1, adr);
}
void Assembler::fisttp_d(const Operand& adr) {
void Assembler::fisttp_d(Operand adr) {
DCHECK(IsEnabled(SSE3));
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
......@@ -2464,16 +2399,14 @@ void Assembler::fisttp_d(const Operand& adr) {
emit_operand(1, adr);
}
void Assembler::fist_s(const Operand& adr) {
void Assembler::fist_s(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDB);
emit_operand(2, adr);
}
void Assembler::fistp_d(const Operand& adr) {
void Assembler::fistp_d(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDF);
......@@ -2555,8 +2488,7 @@ void Assembler::fsub(int i) {
emit_farith(0xDC, 0xE8, i);
}
void Assembler::fisub_s(const Operand& adr) {
void Assembler::fisub_s(Operand adr) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(adr);
emit(0xDA);
......@@ -2734,8 +2666,7 @@ void Assembler::andps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::andps(XMMRegister dst, const Operand& src) {
void Assembler::andps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -2752,8 +2683,7 @@ void Assembler::orps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::orps(XMMRegister dst, const Operand& src) {
void Assembler::orps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -2771,8 +2701,7 @@ void Assembler::xorps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::xorps(XMMRegister dst, const Operand& src) {
void Assembler::xorps(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
......@@ -2790,8 +2719,7 @@ void Assembler::addps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::addps(XMMRegister dst, const Operand& src) {
void Assembler::addps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -2808,8 +2736,7 @@ void Assembler::subps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::subps(XMMRegister dst, const Operand& src) {
void Assembler::subps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -2826,8 +2753,7 @@ void Assembler::mulps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::mulps(XMMRegister dst, const Operand& src) {
void Assembler::mulps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -2844,8 +2770,7 @@ void Assembler::divps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::divps(XMMRegister dst, const Operand& src) {
void Assembler::divps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -2866,8 +2791,7 @@ void Assembler::movd(XMMRegister dst, Register src) {
emit_sse_operand(dst, src);
}
void Assembler::movd(XMMRegister dst, const Operand& src) {
void Assembler::movd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -2930,8 +2854,7 @@ void Assembler::movq(XMMRegister dst, XMMRegister src) {
}
}
void Assembler::movdqa(const Operand& dst, XMMRegister src) {
void Assembler::movdqa(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_rex_64(src, dst);
......@@ -2940,8 +2863,7 @@ void Assembler::movdqa(const Operand& dst, XMMRegister src) {
emit_sse_operand(src, dst);
}
void Assembler::movdqa(XMMRegister dst, const Operand& src) {
void Assembler::movdqa(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_rex_64(dst, src);
......@@ -2950,8 +2872,7 @@ void Assembler::movdqa(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movdqu(const Operand& dst, XMMRegister src) {
void Assembler::movdqu(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_rex_64(src, dst);
......@@ -2960,8 +2881,7 @@ void Assembler::movdqu(const Operand& dst, XMMRegister src) {
emit_sse_operand(src, dst);
}
void Assembler::movdqu(XMMRegister dst, const Operand& src) {
void Assembler::movdqu(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_rex_64(dst, src);
......@@ -2997,7 +2917,7 @@ void Assembler::pextrb(Register dst, XMMRegister src, int8_t imm8) {
emit(imm8);
}
void Assembler::pextrb(const Operand& dst, XMMRegister src, int8_t imm8) {
void Assembler::pextrb(Operand dst, XMMRegister src, int8_t imm8) {
DCHECK(IsEnabled(SSE4_1));
DCHECK(is_uint8(imm8));
EnsureSpace ensure_space(this);
......@@ -3021,7 +2941,7 @@ void Assembler::pinsrw(XMMRegister dst, Register src, int8_t imm8) {
emit(imm8);
}
void Assembler::pinsrw(XMMRegister dst, const Operand& src, int8_t imm8) {
void Assembler::pinsrw(XMMRegister dst, Operand src, int8_t imm8) {
DCHECK(is_uint8(imm8));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -3045,7 +2965,7 @@ void Assembler::pextrw(Register dst, XMMRegister src, int8_t imm8) {
emit(imm8);
}
void Assembler::pextrw(const Operand& dst, XMMRegister src, int8_t imm8) {
void Assembler::pextrw(Operand dst, XMMRegister src, int8_t imm8) {
DCHECK(IsEnabled(SSE4_1));
DCHECK(is_uint8(imm8));
EnsureSpace ensure_space(this);
......@@ -3070,7 +2990,7 @@ void Assembler::pextrd(Register dst, XMMRegister src, int8_t imm8) {
emit(imm8);
}
void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t imm8) {
void Assembler::pextrd(Operand dst, XMMRegister src, int8_t imm8) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -3094,8 +3014,7 @@ void Assembler::pinsrd(XMMRegister dst, Register src, int8_t imm8) {
emit(imm8);
}
void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t imm8) {
void Assembler::pinsrd(XMMRegister dst, Operand src, int8_t imm8) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -3119,7 +3038,7 @@ void Assembler::pinsrb(XMMRegister dst, Register src, int8_t imm8) {
emit(imm8);
}
void Assembler::pinsrb(XMMRegister dst, const Operand& src, int8_t imm8) {
void Assembler::pinsrb(XMMRegister dst, Operand src, int8_t imm8) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -3144,7 +3063,7 @@ void Assembler::insertps(XMMRegister dst, XMMRegister src, byte imm8) {
emit(imm8);
}
void Assembler::movsd(const Operand& dst, XMMRegister src) {
void Assembler::movsd(Operand dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2); // double
......@@ -3165,8 +3084,7 @@ void Assembler::movsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::movsd(XMMRegister dst, const Operand& src) {
void Assembler::movsd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2); // double
......@@ -3225,8 +3143,7 @@ void Assembler::movapd(XMMRegister dst, XMMRegister src) {
}
}
void Assembler::movupd(XMMRegister dst, const Operand& src) {
void Assembler::movupd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
......@@ -3235,7 +3152,7 @@ void Assembler::movupd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movupd(const Operand& dst, XMMRegister src) {
void Assembler::movupd(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(src, dst);
......@@ -3253,8 +3170,7 @@ void Assembler::addss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::addss(XMMRegister dst, const Operand& src) {
void Assembler::addss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3273,8 +3189,7 @@ void Assembler::subss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::subss(XMMRegister dst, const Operand& src) {
void Assembler::subss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3293,8 +3208,7 @@ void Assembler::mulss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::mulss(XMMRegister dst, const Operand& src) {
void Assembler::mulss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3313,8 +3227,7 @@ void Assembler::divss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::divss(XMMRegister dst, const Operand& src) {
void Assembler::divss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3333,8 +3246,7 @@ void Assembler::maxss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::maxss(XMMRegister dst, const Operand& src) {
void Assembler::maxss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3353,8 +3265,7 @@ void Assembler::minss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::minss(XMMRegister dst, const Operand& src) {
void Assembler::minss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3373,8 +3284,7 @@ void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::sqrtss(XMMRegister dst, const Operand& src) {
void Assembler::sqrtss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF3);
emit_optional_rex_32(dst, src);
......@@ -3393,8 +3303,7 @@ void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
void Assembler::ucomiss(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
......@@ -3414,8 +3323,7 @@ void Assembler::movss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::movss(XMMRegister dst, const Operand& src) {
void Assembler::movss(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3); // single
......@@ -3425,8 +3333,7 @@ void Assembler::movss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movss(const Operand& src, XMMRegister dst) {
void Assembler::movss(Operand src, XMMRegister dst) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3); // single
......@@ -3529,7 +3436,7 @@ void Assembler::cmpps(XMMRegister dst, XMMRegister src, int8_t cmp) {
emit(cmp);
}
void Assembler::cmpps(XMMRegister dst, const Operand& src, int8_t cmp) {
void Assembler::cmpps(XMMRegister dst, Operand src, int8_t cmp) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -3548,7 +3455,7 @@ void Assembler::cmppd(XMMRegister dst, XMMRegister src, int8_t cmp) {
emit(cmp);
}
void Assembler::cmppd(XMMRegister dst, const Operand& src, int8_t cmp) {
void Assembler::cmppd(XMMRegister dst, Operand src, int8_t cmp) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x66);
......@@ -3558,7 +3465,7 @@ void Assembler::cmppd(XMMRegister dst, const Operand& src, int8_t cmp) {
emit(cmp);
}
void Assembler::cvttss2si(Register dst, const Operand& src) {
void Assembler::cvttss2si(Register dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -3579,8 +3486,7 @@ void Assembler::cvttss2si(Register dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvttsd2si(Register dst, const Operand& src) {
void Assembler::cvttsd2si(Register dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -3612,8 +3518,7 @@ void Assembler::cvttss2siq(Register dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvttss2siq(Register dst, const Operand& src) {
void Assembler::cvttss2siq(Register dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -3634,8 +3539,7 @@ void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvttsd2siq(Register dst, const Operand& src) {
void Assembler::cvttsd2siq(Register dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -3645,8 +3549,7 @@ void Assembler::cvttsd2siq(Register dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
void Assembler::cvtlsi2sd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -3667,8 +3570,7 @@ void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtlsi2ss(XMMRegister dst, const Operand& src) {
void Assembler::cvtlsi2ss(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -3688,8 +3590,7 @@ void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtqsi2ss(XMMRegister dst, const Operand& src) {
void Assembler::cvtqsi2ss(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -3710,8 +3611,7 @@ void Assembler::cvtqsi2ss(XMMRegister dst, Register src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
void Assembler::cvtqsi2sd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -3743,8 +3643,7 @@ void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
void Assembler::cvtss2sd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -3765,8 +3664,7 @@ void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
void Assembler::cvtsd2ss(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -3808,8 +3706,7 @@ void Assembler::addsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::addsd(XMMRegister dst, const Operand& src) {
void Assembler::addsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3828,8 +3725,7 @@ void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::mulsd(XMMRegister dst, const Operand& src) {
void Assembler::mulsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3848,8 +3744,7 @@ void Assembler::subsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::subsd(XMMRegister dst, const Operand& src) {
void Assembler::subsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3868,8 +3763,7 @@ void Assembler::divsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::divsd(XMMRegister dst, const Operand& src) {
void Assembler::divsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3888,8 +3782,7 @@ void Assembler::maxsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::maxsd(XMMRegister dst, const Operand& src) {
void Assembler::maxsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3908,8 +3801,7 @@ void Assembler::minsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::minsd(XMMRegister dst, const Operand& src) {
void Assembler::minsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -3928,8 +3820,7 @@ void Assembler::andpd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::andpd(XMMRegister dst, const Operand& src) {
void Assembler::andpd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
......@@ -3948,8 +3839,7 @@ void Assembler::orpd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::orpd(XMMRegister dst, const Operand& src) {
void Assembler::orpd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
......@@ -3969,8 +3859,7 @@ void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::xorpd(XMMRegister dst, const Operand& src) {
void Assembler::xorpd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -3991,8 +3880,7 @@ void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
void Assembler::sqrtsd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -4011,7 +3899,7 @@ void Assembler::haddps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::haddps(XMMRegister dst, const Operand& src) {
void Assembler::haddps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
......@@ -4030,8 +3918,7 @@ void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
void Assembler::ucomisd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0x66);
......@@ -4111,7 +3998,7 @@ void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::punpckldq(XMMRegister dst, const Operand& src) {
void Assembler::punpckldq(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
......@@ -4140,9 +4027,8 @@ void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
Operand src2) {
DCHECK(IsEnabled(FMA3));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1);
......@@ -4160,9 +4046,8 @@ void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
Operand src2) {
DCHECK(IsEnabled(FMA3));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0);
......@@ -4180,8 +4065,7 @@ void Assembler::vmovd(XMMRegister dst, Register src) {
emit_sse_operand(dst, src);
}
void Assembler::vmovd(XMMRegister dst, const Operand& src) {
void Assembler::vmovd(XMMRegister dst, Operand src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kL128, k66, k0F, kW0);
......@@ -4209,8 +4093,7 @@ void Assembler::vmovq(XMMRegister dst, Register src) {
emit_sse_operand(dst, src);
}
void Assembler::vmovq(XMMRegister dst, const Operand& src) {
void Assembler::vmovq(XMMRegister dst, Operand src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kL128, k66, k0F, kW1);
......@@ -4238,9 +4121,8 @@ void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2, SIMDPrefix pp, LeadingOpcode m,
VexW w) {
void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
SIMDPrefix pp, LeadingOpcode m, VexW w) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, src1, src2, kLIG, pp, m, w);
......@@ -4258,9 +4140,7 @@ void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, src1, src2, kL128, kNone, k0F, kWIG);
......@@ -4278,9 +4158,7 @@ void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, src1, src2, kL128, k66, k0F, kWIG);
......@@ -4297,8 +4175,7 @@ void Assembler::vucomiss(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::vucomiss(XMMRegister dst, const Operand& src) {
void Assembler::vucomiss(XMMRegister dst, Operand src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, xmm0, src, kLIG, kNone, k0F, kWIG);
......@@ -4316,9 +4193,7 @@ void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(dst, src1, src2, kLIG, kF3, k0F, kWIG);
......@@ -4335,8 +4210,7 @@ void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) {
emit_modrm(reg, rm);
}
void Assembler::bmi1q(byte op, Register reg, Register vreg, const Operand& rm) {
void Assembler::bmi1q(byte op, Register reg, Register vreg, Operand rm) {
DCHECK(IsEnabled(BMI1));
EnsureSpace ensure_space(this);
emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1);
......@@ -4353,8 +4227,7 @@ void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) {
emit_modrm(reg, rm);
}
void Assembler::bmi1l(byte op, Register reg, Register vreg, const Operand& rm) {
void Assembler::bmi1l(byte op, Register reg, Register vreg, Operand rm) {
DCHECK(IsEnabled(BMI1));
EnsureSpace ensure_space(this);
emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0);
......@@ -4373,8 +4246,7 @@ void Assembler::tzcntq(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::tzcntq(Register dst, const Operand& src) {
void Assembler::tzcntq(Register dst, Operand src) {
DCHECK(IsEnabled(BMI1));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -4395,8 +4267,7 @@ void Assembler::tzcntl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::tzcntl(Register dst, const Operand& src) {
void Assembler::tzcntl(Register dst, Operand src) {
DCHECK(IsEnabled(BMI1));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -4417,8 +4288,7 @@ void Assembler::lzcntq(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::lzcntq(Register dst, const Operand& src) {
void Assembler::lzcntq(Register dst, Operand src) {
DCHECK(IsEnabled(LZCNT));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -4439,8 +4309,7 @@ void Assembler::lzcntl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::lzcntl(Register dst, const Operand& src) {
void Assembler::lzcntl(Register dst, Operand src) {
DCHECK(IsEnabled(LZCNT));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -4461,8 +4330,7 @@ void Assembler::popcntq(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::popcntq(Register dst, const Operand& src) {
void Assembler::popcntq(Register dst, Operand src) {
DCHECK(IsEnabled(POPCNT));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -4483,8 +4351,7 @@ void Assembler::popcntl(Register dst, Register src) {
emit_modrm(dst, src);
}
void Assembler::popcntl(Register dst, const Operand& src) {
void Assembler::popcntl(Register dst, Operand src) {
DCHECK(IsEnabled(POPCNT));
EnsureSpace ensure_space(this);
emit(0xF3);
......@@ -4504,9 +4371,8 @@ void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg,
emit_modrm(reg, rm);
}
void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg,
const Operand& rm) {
Operand rm) {
DCHECK(IsEnabled(BMI2));
EnsureSpace ensure_space(this);
emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1);
......@@ -4524,9 +4390,8 @@ void Assembler::bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg,
emit_modrm(reg, rm);
}
void Assembler::bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg,
const Operand& rm) {
Operand rm) {
DCHECK(IsEnabled(BMI2));
EnsureSpace ensure_space(this);
emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW0);
......@@ -4546,8 +4411,7 @@ void Assembler::rorxq(Register dst, Register src, byte imm8) {
emit(imm8);
}
void Assembler::rorxq(Register dst, const Operand& src, byte imm8) {
void Assembler::rorxq(Register dst, Operand src, byte imm8) {
DCHECK(IsEnabled(BMI2));
DCHECK(is_uint8(imm8));
Register vreg = Register::from_code<0>(); // VEX.vvvv unused
......@@ -4570,8 +4434,7 @@ void Assembler::rorxl(Register dst, Register src, byte imm8) {
emit(imm8);
}
void Assembler::rorxl(Register dst, const Operand& src, byte imm8) {
void Assembler::rorxl(Register dst, Operand src, byte imm8) {
DCHECK(IsEnabled(BMI2));
DCHECK(is_uint8(imm8));
Register vreg = Register::from_code<0>(); // VEX.vvvv unused
......@@ -4595,7 +4458,7 @@ void Assembler::minps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::minps(XMMRegister dst, const Operand& src) {
void Assembler::minps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4611,7 +4474,7 @@ void Assembler::maxps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::maxps(XMMRegister dst, const Operand& src) {
void Assembler::maxps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4627,7 +4490,7 @@ void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, const Operand& src) {
void Assembler::rcpps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4643,7 +4506,7 @@ void Assembler::rsqrtps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::rsqrtps(XMMRegister dst, const Operand& src) {
void Assembler::rsqrtps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4659,7 +4522,7 @@ void Assembler::sqrtps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::sqrtps(XMMRegister dst, const Operand& src) {
void Assembler::sqrtps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4675,7 +4538,7 @@ void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) {
void Assembler::cvtdq2ps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4699,7 +4562,7 @@ void Assembler::movups(XMMRegister dst, XMMRegister src) {
}
}
void Assembler::movups(XMMRegister dst, const Operand& src) {
void Assembler::movups(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
......@@ -4707,7 +4570,7 @@ void Assembler::movups(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movups(const Operand& dst, XMMRegister src) {
void Assembler::movups(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(src, dst);
emit(0x0F);
......@@ -4725,7 +4588,7 @@ void Assembler::sse2_instr(XMMRegister dst, XMMRegister src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::sse2_instr(XMMRegister dst, const Operand& src, byte prefix,
void Assembler::sse2_instr(XMMRegister dst, Operand src, byte prefix,
byte escape, byte opcode) {
EnsureSpace ensure_space(this);
emit(prefix);
......@@ -4747,7 +4610,7 @@ void Assembler::ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::ssse3_instr(XMMRegister dst, const Operand& src, byte prefix,
void Assembler::ssse3_instr(XMMRegister dst, Operand src, byte prefix,
byte escape1, byte escape2, byte opcode) {
DCHECK(IsEnabled(SSSE3));
EnsureSpace ensure_space(this);
......@@ -4771,7 +4634,7 @@ void Assembler::sse4_instr(XMMRegister dst, XMMRegister src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
void Assembler::sse4_instr(XMMRegister dst, Operand src, byte prefix,
byte escape1, byte escape2, byte opcode) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
......@@ -4783,7 +4646,7 @@ void Assembler::sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::lddqu(XMMRegister dst, const Operand& src) {
void Assembler::lddqu(XMMRegister dst, Operand src) {
DCHECK(IsEnabled(SSE3));
EnsureSpace ensure_space(this);
emit(0xF2);
......@@ -4833,7 +4696,7 @@ void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
emit(shuffle);
}
void Assembler::pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle) {
void Assembler::pshufd(XMMRegister dst, Operand src, uint8_t shuffle) {
EnsureSpace ensure_space(this);
emit(0x66);
emit_optional_rex_32(dst, src);
......@@ -4843,13 +4706,12 @@ void Assembler::pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle) {
emit(shuffle);
}
void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
void Assembler::emit_sse_operand(XMMRegister reg, Operand adr) {
Register ireg = Register::from_code(reg.code());
emit_operand(ireg, adr);
}
void Assembler::emit_sse_operand(Register reg, const Operand& adr) {
void Assembler::emit_sse_operand(Register reg, Operand adr) {
emit_operand(reg, adr);
}
......
src/x64/assembler-x64.h
View file @ 0237747a
......@@ -322,7 +322,7 @@ class Immediate BASE_EMBEDDED {
// -----------------------------------------------------------------------------
// Machine instruction Operands
enum ScaleFactor {
enum ScaleFactor : int8_t {
times_1 = 0,
times_2 = 1,
times_4 = 2,
......@@ -331,8 +331,7 @@ enum ScaleFactor {
times_pointer_size = (kPointerSize == 8) ? times_8 : times_4
};
class Operand BASE_EMBEDDED {
class Operand {
public:
// [base + disp/r]
Operand(Register base, int32_t disp);
......@@ -351,7 +350,7 @@ class Operand BASE_EMBEDDED {
// Offset from existing memory operand.
// Offset is added to existing displacement as 32-bit signed values and
// this must not overflow.
Operand(const Operand& base, int32_t offset);
Operand(Operand base, int32_t offset);
// [rip + disp/r]
explicit Operand(Label* label, int addend = 0);
......@@ -389,8 +388,13 @@ class Operand BASE_EMBEDDED {
inline void set_disp32(int disp);
inline void set_disp64(int64_t disp); // for labels.
// TODO(clemensh): Get rid of this friendship, or make Operand immutable.
friend class Assembler;
};
static_assert(sizeof(Operand) <= 2 * kPointerSize,
"Operand must be small enough to pass it by value");
static_assert(IS_TRIVIALLY_COPYABLE(Operand),
"Operand must be trivially copyable to pass it by value");
#define ASSEMBLER_INSTRUCTION_LIST(V) \
V(add) \
......@@ -618,29 +622,29 @@ class Assembler : public AssemblerBase {
// 32 bit value, the normal push will optimize the 8 bit case.
void pushq_imm32(int32_t imm32);
void pushq(Register src);
void pushq(const Operand& src);
void pushq(Operand src);
void popq(Register dst);
void popq(const Operand& dst);
void popq(Operand dst);
void enter(Immediate size);
void leave();
// Moves
void movb(Register dst, const Operand& src);
void movb(Register dst, Operand src);
void movb(Register dst, Immediate imm);
void movb(const Operand& dst, Register src);
void movb(const Operand& dst, Immediate imm);
void movb(Operand dst, Register src);
void movb(Operand dst, Immediate imm);
// Move the low 16 bits of a 64-bit register value to a 16-bit
// memory location.
void movw(Register dst, const Operand& src);
void movw(const Operand& dst, Register src);
void movw(const Operand& dst, Immediate imm);
void movw(Register dst, Operand src);
void movw(Operand dst, Register src);
void movw(Operand dst, Immediate imm);
// Move the offset of the label location relative to the current
// position (after the move) to the destination.
void movl(const Operand& dst, Label* src);
void movl(Operand dst, Label* src);
// Loads a pointer into a register with a relocation mode.
void movp(Register dst, void* ptr, RelocInfo::Mode rmode);
......@@ -661,15 +665,15 @@ class Assembler : public AssemblerBase {
RelocInfo::Mode rmode = RelocInfo::NONE);
void movsxbl(Register dst, Register src);
void movsxbl(Register dst, const Operand& src);
void movsxbl(Register dst, Operand src);
void movsxbq(Register dst, Register src);
void movsxbq(Register dst, const Operand& src);
void movsxbq(Register dst, Operand src);
void movsxwl(Register dst, Register src);
void movsxwl(Register dst, const Operand& src);
void movsxwl(Register dst, Operand src);
void movsxwq(Register dst, Register src);
void movsxwq(Register dst, const Operand& src);
void movsxwq(Register dst, Operand src);
void movsxlq(Register dst, Register src);
void movsxlq(Register dst, const Operand& src);
void movsxlq(Register dst, Operand src);
// Repeated moves.
......@@ -685,9 +689,9 @@ class Assembler : public AssemblerBase {
// Conditional moves.
void cmovq(Condition cc, Register dst, Register src);
void cmovq(Condition cc, Register dst, const Operand& src);
void cmovq(Condition cc, Register dst, Operand src);
void cmovl(Condition cc, Register dst, Register src);
void cmovl(Condition cc, Register dst, const Operand& src);
void cmovl(Condition cc, Register dst, Operand src);
void cmpb(Register dst, Immediate src) {
immediate_arithmetic_op_8(0x7, dst, src);
......@@ -699,19 +703,15 @@ class Assembler : public AssemblerBase {
arithmetic_op_8(0x3A, dst, src);
}
void cmpb(Register dst, const Operand& src) {
arithmetic_op_8(0x3A, dst, src);
}
void cmpb(Register dst, Operand src) { arithmetic_op_8(0x3A, dst, src); }
void cmpb(const Operand& dst, Register src) {
arithmetic_op_8(0x38, src, dst);
}
void cmpb(Operand dst, Register src) { arithmetic_op_8(0x38, src, dst); }
void cmpb(const Operand& dst, Immediate src) {
void cmpb(Operand dst, Immediate src) {
immediate_arithmetic_op_8(0x7, dst, src);
}
void cmpw(const Operand& dst, Immediate src) {
void cmpw(Operand dst, Immediate src) {
immediate_arithmetic_op_16(0x7, dst, src);
}
......@@ -719,37 +719,33 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op_16(0x7, dst, src);
}
void cmpw(Register dst, const Operand& src) {
arithmetic_op_16(0x3B, dst, src);
}
void cmpw(Register dst, Operand src) { arithmetic_op_16(0x3B, dst, src); }
void cmpw(Register dst, Register src) {
arithmetic_op_16(0x3B, dst, src);
}
void cmpw(const Operand& dst, Register src) {
arithmetic_op_16(0x39, src, dst);
}
void cmpw(Operand dst, Register src) { arithmetic_op_16(0x39, src, dst); }
void testb(Register reg, const Operand& op) { testb(op, reg); }
void testb(Register reg, Operand op) { testb(op, reg); }
void testw(Register reg, const Operand& op) { testw(op, reg); }
void testw(Register reg, Operand op) { testw(op, reg); }
void andb(Register dst, Immediate src) {
immediate_arithmetic_op_8(0x4, dst, src);
}
void decb(Register dst);
void decb(const Operand& dst);
void decb(Operand dst);
// Lock prefix.
void lock();
void xchgb(Register reg, const Operand& op);
void xchgw(Register reg, const Operand& op);
void xchgb(Register reg, Operand op);
void xchgw(Register reg, Operand op);
void cmpxchgb(const Operand& dst, Register src);
void cmpxchgw(const Operand& dst, Register src);
void cmpxchgb(Operand dst, Register src);
void cmpxchgw(Operand dst, Register src);
// Sign-extends rax into rdx:rax.
void cqo();
......@@ -758,7 +754,7 @@ class Assembler : public AssemblerBase {
// Multiply eax by src, put the result in edx:eax.
void mull(Register src);
void mull(const Operand& src);
void mull(Operand src);
// Multiply rax by src, put the result in rdx:rax.
void mulq(Register src);
......@@ -818,25 +814,25 @@ class Assembler : public AssemblerBase {
void testb(Register dst, Register src);
void testb(Register reg, Immediate mask);
void testb(const Operand& op, Immediate mask);
void testb(const Operand& op, Register reg);
void testb(Operand op, Immediate mask);
void testb(Operand op, Register reg);
void testw(Register dst, Register src);
void testw(Register reg, Immediate mask);
void testw(const Operand& op, Immediate mask);
void testw(const Operand& op, Register reg);
void testw(Operand op, Immediate mask);
void testw(Operand op, Register reg);
// Bit operations.
void bt(const Operand& dst, Register src);
void bts(const Operand& dst, Register src);
void bt(Operand dst, Register src);
void bts(Operand dst, Register src);
void bsrq(Register dst, Register src);
void bsrq(Register dst, const Operand& src);
void bsrq(Register dst, Operand src);
void bsrl(Register dst, Register src);
void bsrl(Register dst, const Operand& src);
void bsrl(Register dst, Operand src);
void bsfq(Register dst, Register src);
void bsfq(Register dst, const Operand& src);
void bsfq(Register dst, Operand src);
void bsfl(Register dst, Register src);
void bsfl(Register dst, const Operand& src);
void bsfl(Register dst, Operand src);
// Miscellaneous
void clc();
......@@ -850,7 +846,7 @@ class Assembler : public AssemblerBase {
void setcc(Condition cc, Register reg);
void pshufw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void pshufw(XMMRegister dst, const Operand& src, uint8_t shuffle);
void pshufw(XMMRegister dst, Operand src, uint8_t shuffle);
// Label operations & relative jumps (PPUM Appendix D)
//
......@@ -897,7 +893,7 @@ class Assembler : public AssemblerBase {
// Jump near absolute indirect (r64)
void jmp(Register adr);
void jmp(const Operand& src);
void jmp(Operand src);
// Conditional jumps
void j(Condition cc,
......@@ -914,23 +910,23 @@ class Assembler : public AssemblerBase {
void fldpi();
void fldln2();
void fld_s(const Operand& adr);
void fld_d(const Operand& adr);
void fld_s(Operand adr);
void fld_d(Operand adr);
void fstp_s(const Operand& adr);
void fstp_d(const Operand& adr);
void fstp_s(Operand adr);
void fstp_d(Operand adr);
void fstp(int index);
void fild_s(const Operand& adr);
void fild_d(const Operand& adr);
void fild_s(Operand adr);
void fild_d(Operand adr);
void fist_s(const Operand& adr);
void fist_s(Operand adr);
void fistp_s(const Operand& adr);
void fistp_d(const Operand& adr);
void fistp_s(Operand adr);
void fistp_d(Operand adr);
void fisttp_s(const Operand& adr);
void fisttp_d(const Operand& adr);
void fisttp_s(Operand adr);
void fisttp_d(Operand adr);
void fabs();
void fchs();
......@@ -940,7 +936,7 @@ class Assembler : public AssemblerBase {
void fmul(int i);
void fdiv(int i);
void fisub_s(const Operand& adr);
void fisub_s(Operand adr);
void faddp(int i = 1);
void fsubp(int i = 1);
......@@ -979,24 +975,24 @@ class Assembler : public AssemblerBase {
// SSE instructions
void addss(XMMRegister dst, XMMRegister src);
void addss(XMMRegister dst, const Operand& src);
void addss(XMMRegister dst, Operand src);
void subss(XMMRegister dst, XMMRegister src);
void subss(XMMRegister dst, const Operand& src);
void subss(XMMRegister dst, Operand src);
void mulss(XMMRegister dst, XMMRegister src);
void mulss(XMMRegister dst, const Operand& src);
void mulss(XMMRegister dst, Operand src);
void divss(XMMRegister dst, XMMRegister src);
void divss(XMMRegister dst, const Operand& src);
void divss(XMMRegister dst, Operand src);
void maxss(XMMRegister dst, XMMRegister src);
void maxss(XMMRegister dst, const Operand& src);
void maxss(XMMRegister dst, Operand src);
void minss(XMMRegister dst, XMMRegister src);
void minss(XMMRegister dst, const Operand& src);
void minss(XMMRegister dst, Operand src);
void sqrtss(XMMRegister dst, XMMRegister src);
void sqrtss(XMMRegister dst, const Operand& src);
void sqrtss(XMMRegister dst, Operand src);
void ucomiss(XMMRegister dst, XMMRegister src);
void ucomiss(XMMRegister dst, const Operand& src);
void ucomiss(XMMRegister dst, Operand src);
void movaps(XMMRegister dst, XMMRegister src);
// Don't use this unless it's important to keep the
......@@ -1005,48 +1001,48 @@ class Assembler : public AssemblerBase {
// values in xmm registers.
void movss(XMMRegister dst, XMMRegister src);
void movss(XMMRegister dst, const Operand& src);
void movss(const Operand& dst, XMMRegister src);
void movss(XMMRegister dst, Operand src);
void movss(Operand dst, XMMRegister src);
void shufps(XMMRegister dst, XMMRegister src, byte imm8);
void cvttss2si(Register dst, const Operand& src);
void cvttss2si(Register dst, Operand src);
void cvttss2si(Register dst, XMMRegister src);
void cvtlsi2ss(XMMRegister dst, const Operand& src);
void cvtlsi2ss(XMMRegister dst, Operand src);
void cvtlsi2ss(XMMRegister dst, Register src);
void andps(XMMRegister dst, XMMRegister src);
void andps(XMMRegister dst, const Operand& src);
void andps(XMMRegister dst, Operand src);
void orps(XMMRegister dst, XMMRegister src);
void orps(XMMRegister dst, const Operand& src);
void orps(XMMRegister dst, Operand src);
void xorps(XMMRegister dst, XMMRegister src);
void xorps(XMMRegister dst, const Operand& src);
void xorps(XMMRegister dst, Operand src);
void addps(XMMRegister dst, XMMRegister src);
void addps(XMMRegister dst, const Operand& src);
void addps(XMMRegister dst, Operand src);
void subps(XMMRegister dst, XMMRegister src);
void subps(XMMRegister dst, const Operand& src);
void subps(XMMRegister dst, Operand src);
void mulps(XMMRegister dst, XMMRegister src);
void mulps(XMMRegister dst, const Operand& src);
void mulps(XMMRegister dst, Operand src);
void divps(XMMRegister dst, XMMRegister src);
void divps(XMMRegister dst, const Operand& src);
void divps(XMMRegister dst, Operand src);
void movmskps(Register dst, XMMRegister src);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
SIMDPrefix pp, LeadingOpcode m, VexW w);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2,
void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
SIMDPrefix pp, LeadingOpcode m, VexW w);
// SSE2 instructions
void sse2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape,
byte opcode);
void sse2_instr(XMMRegister dst, const Operand& src, byte prefix, byte escape,
void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape,
byte opcode);
#define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
} \
void instruction(XMMRegister dst, const Operand& src) { \
void instruction(XMMRegister dst, Operand src) { \
sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
}
......@@ -1057,8 +1053,7 @@ class Assembler : public AssemblerBase {
void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
} \
void v##instruction(XMMRegister dst, XMMRegister src1, \
const Operand& src2) { \
void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
}
......@@ -1066,20 +1061,20 @@ class Assembler : public AssemblerBase {
#undef DECLARE_SSE2_AVX_INSTRUCTION
// SSE3
void lddqu(XMMRegister dst, const Operand& src);
void lddqu(XMMRegister dst, Operand src);
// SSSE3
void ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode);
void ssse3_instr(XMMRegister dst, const Operand& src, byte prefix,
byte escape1, byte escape2, byte opcode);
void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
#define DECLARE_SSSE3_INSTRUCTION(instruction, prefix, escape1, escape2, \
opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
} \
void instruction(XMMRegister dst, const Operand& src) { \
void instruction(XMMRegister dst, Operand src) { \
ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
......@@ -1089,14 +1084,14 @@ class Assembler : public AssemblerBase {
// SSE4
void sse4_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode);
void sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
byte escape1, byte escape2, byte opcode);
void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
#define DECLARE_SSE4_INSTRUCTION(instruction, prefix, escape1, escape2, \
opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
} \
void instruction(XMMRegister dst, const Operand& src) { \
void instruction(XMMRegister dst, Operand src) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
......@@ -1108,8 +1103,7 @@ class Assembler : public AssemblerBase {
void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
} \
void v##instruction(XMMRegister dst, XMMRegister src1, \
const Operand& src2) { \
void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
}
......@@ -1118,7 +1112,7 @@ class Assembler : public AssemblerBase {
#undef DECLARE_SSE34_AVX_INSTRUCTION
void movd(XMMRegister dst, Register src);
void movd(XMMRegister dst, const Operand& src);
void movd(XMMRegister dst, Operand src);
void movd(Register dst, XMMRegister src);
void movq(XMMRegister dst, Register src);
void movq(Register dst, XMMRegister src);
......@@ -1130,18 +1124,18 @@ class Assembler : public AssemblerBase {
// values in xmm registers.
void movsd(XMMRegister dst, XMMRegister src);
void movsd(const Operand& dst, XMMRegister src);
void movsd(XMMRegister dst, const Operand& src);
void movsd(Operand dst, XMMRegister src);
void movsd(XMMRegister dst, Operand src);
void movdqa(const Operand& dst, XMMRegister src);
void movdqa(XMMRegister dst, const Operand& src);
void movdqa(Operand dst, XMMRegister src);
void movdqa(XMMRegister dst, Operand src);
void movdqu(const Operand& dst, XMMRegister src);
void movdqu(XMMRegister dst, const Operand& src);
void movdqu(Operand dst, XMMRegister src);
void movdqu(XMMRegister dst, Operand src);
void movapd(XMMRegister dst, XMMRegister src);
void movupd(XMMRegister dst, const Operand& src);
void movupd(const Operand& dst, XMMRegister src);
void movupd(XMMRegister dst, Operand src);
void movupd(Operand dst, XMMRegister src);
void psllq(XMMRegister reg, byte imm8);
void psrlq(XMMRegister reg, byte imm8);
......@@ -1152,98 +1146,96 @@ class Assembler : public AssemblerBase {
void psraw(XMMRegister reg, byte imm8);
void psrad(XMMRegister reg, byte imm8);
void cvttsd2si(Register dst, const Operand& src);
void cvttsd2si(Register dst, Operand src);
void cvttsd2si(Register dst, XMMRegister src);
void cvttss2siq(Register dst, XMMRegister src);
void cvttss2siq(Register dst, const Operand& src);
void cvttss2siq(Register dst, Operand src);
void cvttsd2siq(Register dst, XMMRegister src);
void cvttsd2siq(Register dst, const Operand& src);
void cvttsd2siq(Register dst, Operand src);
void cvtlsi2sd(XMMRegister dst, const Operand& src);
void cvtlsi2sd(XMMRegister dst, Operand src);
void cvtlsi2sd(XMMRegister dst, Register src);
void cvtqsi2ss(XMMRegister dst, const Operand& src);
void cvtqsi2ss(XMMRegister dst, Operand src);
void cvtqsi2ss(XMMRegister dst, Register src);
void cvtqsi2sd(XMMRegister dst, const Operand& src);
void cvtqsi2sd(XMMRegister dst, Operand src);
void cvtqsi2sd(XMMRegister dst, Register src);
void cvtss2sd(XMMRegister dst, XMMRegister src);
void cvtss2sd(XMMRegister dst, const Operand& src);
void cvtss2sd(XMMRegister dst, Operand src);
void cvtsd2ss(XMMRegister dst, XMMRegister src);
void cvtsd2ss(XMMRegister dst, const Operand& src);
void cvtsd2ss(XMMRegister dst, Operand src);
void cvtsd2si(Register dst, XMMRegister src);
void cvtsd2siq(Register dst, XMMRegister src);
void addsd(XMMRegister dst, XMMRegister src);
void addsd(XMMRegister dst, const Operand& src);
void addsd(XMMRegister dst, Operand src);
void subsd(XMMRegister dst, XMMRegister src);
void subsd(XMMRegister dst, const Operand& src);
void subsd(XMMRegister dst, Operand src);
void mulsd(XMMRegister dst, XMMRegister src);
void mulsd(XMMRegister dst, const Operand& src);
void mulsd(XMMRegister dst, Operand src);
void divsd(XMMRegister dst, XMMRegister src);
void divsd(XMMRegister dst, const Operand& src);
void divsd(XMMRegister dst, Operand src);
void maxsd(XMMRegister dst, XMMRegister src);
void maxsd(XMMRegister dst, const Operand& src);
void maxsd(XMMRegister dst, Operand src);
void minsd(XMMRegister dst, XMMRegister src);
void minsd(XMMRegister dst, const Operand& src);
void minsd(XMMRegister dst, Operand src);
void andpd(XMMRegister dst, XMMRegister src);
void andpd(XMMRegister dst, const Operand& src);
void andpd(XMMRegister dst, Operand src);
void orpd(XMMRegister dst, XMMRegister src);
void orpd(XMMRegister dst, const Operand& src);
void orpd(XMMRegister dst, Operand src);
void xorpd(XMMRegister dst, XMMRegister src);
void xorpd(XMMRegister dst, const Operand& src);
void xorpd(XMMRegister dst, Operand src);
void sqrtsd(XMMRegister dst, XMMRegister src);
void sqrtsd(XMMRegister dst, const Operand& src);
void sqrtsd(XMMRegister dst, Operand src);
void haddps(XMMRegister dst, XMMRegister src);
void haddps(XMMRegister dst, const Operand& src);
void haddps(XMMRegister dst, Operand src);
void ucomisd(XMMRegister dst, XMMRegister src);
void ucomisd(XMMRegister dst, const Operand& src);
void ucomisd(XMMRegister dst, Operand src);
void cmpltsd(XMMRegister dst, XMMRegister src);
void movmskpd(Register dst, XMMRegister src);
void punpckldq(XMMRegister dst, XMMRegister src);
void punpckldq(XMMRegister dst, const Operand& src);
void punpckldq(XMMRegister dst, Operand src);
void punpckhdq(XMMRegister dst, XMMRegister src);
// SSE 4.1 instruction
void insertps(XMMRegister dst, XMMRegister src, byte imm8);
void extractps(Register dst, XMMRegister src, byte imm8);
void pextrb(Register dst, XMMRegister src, int8_t imm8);
void pextrb(const Operand& dst, XMMRegister src, int8_t imm8);
void pextrb(Operand dst, XMMRegister src, int8_t imm8);
void pextrw(Register dst, XMMRegister src, int8_t imm8);
void pextrw(const Operand& dst, XMMRegister src, int8_t imm8);
void pextrw(Operand dst, XMMRegister src, int8_t imm8);
void pextrd(Register dst, XMMRegister src, int8_t imm8);
void pextrd(const Operand& dst, XMMRegister src, int8_t imm8);
void pextrd(Operand dst, XMMRegister src, int8_t imm8);
void pinsrb(XMMRegister dst, Register src, int8_t imm8);
void pinsrb(XMMRegister dst, const Operand& src, int8_t imm8);
void pinsrb(XMMRegister dst, Operand src, int8_t imm8);
void pinsrw(XMMRegister dst, Register src, int8_t imm8);
void pinsrw(XMMRegister dst, const Operand& src, int8_t imm8);
void pinsrw(XMMRegister dst, Operand src, int8_t imm8);
void pinsrd(XMMRegister dst, Register src, int8_t imm8);
void pinsrd(XMMRegister dst, const Operand& src, int8_t imm8);
void pinsrd(XMMRegister dst, Operand src, int8_t imm8);
void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode);
void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
void cmpps(XMMRegister dst, const Operand& src, int8_t cmp);
void cmpps(XMMRegister dst, Operand src, int8_t cmp);
void cmppd(XMMRegister dst, XMMRegister src, int8_t cmp);
void cmppd(XMMRegister dst, const Operand& src, int8_t cmp);
void cmppd(XMMRegister dst, Operand src, int8_t cmp);
#define SSE_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src) { cmpps(dst, src, imm8); } \
void instr##ps(XMMRegister dst, const Operand& src) { \
cmpps(dst, src, imm8); \
} \
void instr##ps(XMMRegister dst, Operand src) { cmpps(dst, src, imm8); } \
void instr##pd(XMMRegister dst, XMMRegister src) { cmppd(dst, src, imm8); } \
void instr##pd(XMMRegister dst, const Operand& src) { cmppd(dst, src, imm8); }
void instr##pd(XMMRegister dst, Operand src) { cmppd(dst, src, imm8); }
SSE_CMP_P(cmpeq, 0x0);
SSE_CMP_P(cmplt, 0x1);
......@@ -1255,25 +1247,25 @@ class Assembler : public AssemblerBase {
#undef SSE_CMP_P
void minps(XMMRegister dst, XMMRegister src);
void minps(XMMRegister dst, const Operand& src);
void minps(XMMRegister dst, Operand src);
void maxps(XMMRegister dst, XMMRegister src);
void maxps(XMMRegister dst, const Operand& src);
void maxps(XMMRegister dst, Operand src);
void rcpps(XMMRegister dst, XMMRegister src);
void rcpps(XMMRegister dst, const Operand& src);
void rcpps(XMMRegister dst, Operand src);
void rsqrtps(XMMRegister dst, XMMRegister src);
void rsqrtps(XMMRegister dst, const Operand& src);
void rsqrtps(XMMRegister dst, Operand src);
void sqrtps(XMMRegister dst, XMMRegister src);
void sqrtps(XMMRegister dst, const Operand& src);
void sqrtps(XMMRegister dst, Operand src);
void movups(XMMRegister dst, XMMRegister src);
void movups(XMMRegister dst, const Operand& src);
void movups(const Operand& dst, XMMRegister src);
void movups(XMMRegister dst, Operand src);
void movups(Operand dst, XMMRegister src);
void psrldq(XMMRegister dst, uint8_t shift);
void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle);
void pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
void pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void cvtdq2ps(XMMRegister dst, XMMRegister src);
void cvtdq2ps(XMMRegister dst, const Operand& src);
void cvtdq2ps(XMMRegister dst, Operand src);
// AVX instruction
void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1285,13 +1277,13 @@ class Assembler : public AssemblerBase {
void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmasd(0xb9, dst, src1, src2);
}
void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x99, dst, src1, src2);
}
void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xa9, dst, src1, src2);
}
void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xb9, dst, src1, src2);
}
void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1303,13 +1295,13 @@ class Assembler : public AssemblerBase {
void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmasd(0xbb, dst, src1, src2);
}
void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x9b, dst, src1, src2);
}
void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xab, dst, src1, src2);
}
void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xbb, dst, src1, src2);
}
void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1321,13 +1313,13 @@ class Assembler : public AssemblerBase {
void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmasd(0xbd, dst, src1, src2);
}
void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x9d, dst, src1, src2);
}
void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xad, dst, src1, src2);
}
void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xbd, dst, src1, src2);
}
void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1339,17 +1331,17 @@ class Assembler : public AssemblerBase {
void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmasd(0xbf, dst, src1, src2);
}
void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x9f, dst, src1, src2);
}
void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xaf, dst, src1, src2);
}
void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xbf, dst, src1, src2);
}
void vfmasd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vfmasd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmass(0x99, dst, src1, src2);
......@@ -1360,13 +1352,13 @@ class Assembler : public AssemblerBase {
void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmass(0xb9, dst, src1, src2);
}
void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x99, dst, src1, src2);
}
void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xa9, dst, src1, src2);
}
void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xb9, dst, src1, src2);
}
void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1378,13 +1370,13 @@ class Assembler : public AssemblerBase {
void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmass(0xbb, dst, src1, src2);
}
void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x9b, dst, src1, src2);
}
void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xab, dst, src1, src2);
}
void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xbb, dst, src1, src2);
}
void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1396,13 +1388,13 @@ class Assembler : public AssemblerBase {
void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmass(0xbd, dst, src1, src2);
}
void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x9d, dst, src1, src2);
}
void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xad, dst, src1, src2);
}
void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xbd, dst, src1, src2);
}
void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1414,34 +1406,30 @@ class Assembler : public AssemblerBase {
void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmass(0xbf, dst, src1, src2);
}
void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x9f, dst, src1, src2);
}
void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xaf, dst, src1, src2);
}
void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xbf, dst, src1, src2);
}
void vfmass(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vfmass(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vmovd(XMMRegister dst, Register src);
void vmovd(XMMRegister dst, const Operand& src);
void vmovd(XMMRegister dst, Operand src);
void vmovd(Register dst, XMMRegister src);
void vmovq(XMMRegister dst, Register src);
void vmovq(XMMRegister dst, const Operand& src);
void vmovq(XMMRegister dst, Operand src);
void vmovq(Register dst, XMMRegister src);
void vmovsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x10, dst, src1, src2);
}
void vmovsd(XMMRegister dst, const Operand& src) {
vsd(0x10, dst, xmm0, src);
}
void vmovsd(const Operand& dst, XMMRegister src) {
vsd(0x11, src, xmm0, dst);
}
void vmovsd(XMMRegister dst, Operand src) { vsd(0x10, dst, xmm0, src); }
void vmovsd(Operand dst, XMMRegister src) { vsd(0x11, src, xmm0, dst); }
#define AVX_SP_3(instr, opcode) \
AVX_S_3(instr, opcode) \
......@@ -1455,12 +1443,12 @@ class Assembler : public AssemblerBase {
AVX_3(instr##ps, opcode, vps) \
AVX_3(instr##pd, opcode, vpd)
#define AVX_3(instr, opcode, impl) \
void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
impl(opcode, dst, src1, src2); \
} \
void instr(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
impl(opcode, dst, src1, src2); \
#define AVX_3(instr, opcode, impl) \
void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
impl(opcode, dst, src1, src2); \
} \
void instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
impl(opcode, dst, src1, src2); \
}
AVX_SP_3(vsqrt, 0x51);
......@@ -1491,42 +1479,42 @@ class Assembler : public AssemblerBase {
void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG);
}
void vcvtss2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vcvtss2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW0);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF2, k0F, kW0);
}
void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW0);
}
void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF3, k0F, kW0);
}
void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW1);
}
void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF3, k0F, kW1);
}
void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW1);
}
void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF2, k0F, kW1);
}
void vcvttss2si(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0);
}
void vcvttss2si(Register dst, const Operand& src) {
void vcvttss2si(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0);
}
......@@ -1534,7 +1522,7 @@ class Assembler : public AssemblerBase {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0);
}
void vcvttsd2si(Register dst, const Operand& src) {
void vcvttsd2si(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0);
}
......@@ -1542,7 +1530,7 @@ class Assembler : public AssemblerBase {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1);
}
void vcvttss2siq(Register dst, const Operand& src) {
void vcvttss2siq(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1);
}
......@@ -1550,7 +1538,7 @@ class Assembler : public AssemblerBase {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1);
}
void vcvttsd2siq(Register dst, const Operand& src) {
void vcvttsd2siq(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1);
}
......@@ -1561,7 +1549,7 @@ class Assembler : public AssemblerBase {
void vucomisd(XMMRegister dst, XMMRegister src) {
vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
}
void vucomisd(XMMRegister dst, const Operand& src) {
void vucomisd(XMMRegister dst, Operand src) {
vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
}
void vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2,
......@@ -1578,39 +1566,27 @@ class Assembler : public AssemblerBase {
void vsd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
}
void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vsd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
}
void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x10, dst, src1, src2);
}
void vmovss(XMMRegister dst, const Operand& src) {
vss(0x10, dst, xmm0, src);
}
void vmovss(const Operand& dst, XMMRegister src) {
vss(0x11, src, xmm0, dst);
}
void vmovss(XMMRegister dst, Operand src) { vss(0x10, dst, xmm0, src); }
void vmovss(Operand dst, XMMRegister src) { vss(0x11, src, xmm0, dst); }
void vucomiss(XMMRegister dst, XMMRegister src);
void vucomiss(XMMRegister dst, const Operand& src);
void vucomiss(XMMRegister dst, Operand src);
void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vmovaps(XMMRegister dst, XMMRegister src) { vps(0x28, dst, xmm0, src); }
void vmovups(XMMRegister dst, XMMRegister src) { vps(0x10, dst, xmm0, src); }
void vmovups(XMMRegister dst, const Operand& src) {
vps(0x10, dst, xmm0, src);
}
void vmovups(const Operand& dst, XMMRegister src) {
vps(0x11, src, xmm0, dst);
}
void vmovups(XMMRegister dst, Operand src) { vps(0x10, dst, xmm0, src); }
void vmovups(Operand dst, XMMRegister src) { vps(0x11, src, xmm0, dst); }
void vmovapd(XMMRegister dst, XMMRegister src) { vpd(0x28, dst, xmm0, src); }
void vmovupd(XMMRegister dst, const Operand& src) {
vpd(0x10, dst, xmm0, src);
}
void vmovupd(const Operand& dst, XMMRegister src) {
vpd(0x11, src, xmm0, dst);
}
void vmovupd(XMMRegister dst, Operand src) { vpd(0x10, dst, xmm0, src); }
void vmovupd(Operand dst, XMMRegister src) { vpd(0x11, src, xmm0, dst); }
void vmovmskps(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vps(0x50, idst, xmm0, src);
......@@ -1623,8 +1599,7 @@ class Assembler : public AssemblerBase {
vps(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmpps(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t cmp) {
void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
vps(0xC2, dst, src1, src2);
emit(cmp);
}
......@@ -1632,24 +1607,23 @@ class Assembler : public AssemblerBase {
vpd(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmppd(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t cmp) {
void vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
vpd(0xC2, dst, src1, src2);
emit(cmp);
}
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmppd(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vcmppd(dst, src1, src2, imm8); \
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##ps(XMMRegister dst, XMMRegister src1, Operand src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmppd(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, Operand src2) { \
vcmppd(dst, src1, src2, imm8); \
}
AVX_CMP_P(vcmpeq, 0x0);
......@@ -1661,7 +1635,7 @@ class Assembler : public AssemblerBase {
#undef AVX_CMP_P
void vlddqu(XMMRegister dst, const Operand& src) {
void vlddqu(XMMRegister dst, Operand src) {
vinstr(0xF0, dst, xmm0, src, kF2, k0F, kWIG);
}
void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8) {
......@@ -1693,7 +1667,7 @@ class Assembler : public AssemblerBase {
vinstr(0x14, src, xmm0, idst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrb(const Operand& dst, XMMRegister src, int8_t imm8) {
void vpextrb(Operand dst, XMMRegister src, int8_t imm8) {
vinstr(0x14, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
......@@ -1702,7 +1676,7 @@ class Assembler : public AssemblerBase {
vinstr(0xc5, idst, xmm0, src, k66, k0F, kW0);
emit(imm8);
}
void vpextrw(const Operand& dst, XMMRegister src, int8_t imm8) {
void vpextrw(Operand dst, XMMRegister src, int8_t imm8) {
vinstr(0x15, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
......@@ -1711,7 +1685,7 @@ class Assembler : public AssemblerBase {
vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrd(const Operand& dst, XMMRegister src, int8_t imm8) {
void vpextrd(Operand dst, XMMRegister src, int8_t imm8) {
vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
......@@ -1720,8 +1694,7 @@ class Assembler : public AssemblerBase {
vinstr(0x20, dst, src1, isrc, k66, k0F3A, kW0);
emit(imm8);
}
void vpinsrb(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t imm8) {
void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) {
vinstr(0x20, dst, src1, src2, k66, k0F3A, kW0);
emit(imm8);
}
......@@ -1730,8 +1703,7 @@ class Assembler : public AssemblerBase {
vinstr(0xc4, dst, src1, isrc, k66, k0F, kW0);
emit(imm8);
}
void vpinsrw(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t imm8) {
void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) {
vinstr(0xc4, dst, src1, src2, k66, k0F, kW0);
emit(imm8);
}
......@@ -1740,8 +1712,7 @@ class Assembler : public AssemblerBase {
vinstr(0x22, dst, src1, isrc, k66, k0F3A, kW0);
emit(imm8);
}
void vpinsrd(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t imm8) {
void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) {
vinstr(0x22, dst, src1, src2, k66, k0F3A, kW0);
emit(imm8);
}
......@@ -1751,150 +1722,150 @@ class Assembler : public AssemblerBase {
}
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
// BMI instruction
void andnq(Register dst, Register src1, Register src2) {
bmi1q(0xf2, dst, src1, src2);
}
void andnq(Register dst, Register src1, const Operand& src2) {
void andnq(Register dst, Register src1, Operand src2) {
bmi1q(0xf2, dst, src1, src2);
}
void andnl(Register dst, Register src1, Register src2) {
bmi1l(0xf2, dst, src1, src2);
}
void andnl(Register dst, Register src1, const Operand& src2) {
void andnl(Register dst, Register src1, Operand src2) {
bmi1l(0xf2, dst, src1, src2);
}
void bextrq(Register dst, Register src1, Register src2) {
bmi1q(0xf7, dst, src2, src1);
}
void bextrq(Register dst, const Operand& src1, Register src2) {
void bextrq(Register dst, Operand src1, Register src2) {
bmi1q(0xf7, dst, src2, src1);
}
void bextrl(Register dst, Register src1, Register src2) {
bmi1l(0xf7, dst, src2, src1);
}
void bextrl(Register dst, const Operand& src1, Register src2) {
void bextrl(Register dst, Operand src1, Register src2) {
bmi1l(0xf7, dst, src2, src1);
}
void blsiq(Register dst, Register src) { bmi1q(0xf3, rbx, dst, src); }
void blsiq(Register dst, const Operand& src) { bmi1q(0xf3, rbx, dst, src); }
void blsiq(Register dst, Operand src) { bmi1q(0xf3, rbx, dst, src); }
void blsil(Register dst, Register src) { bmi1l(0xf3, rbx, dst, src); }
void blsil(Register dst, const Operand& src) { bmi1l(0xf3, rbx, dst, src); }
void blsil(Register dst, Operand src) { bmi1l(0xf3, rbx, dst, src); }
void blsmskq(Register dst, Register src) { bmi1q(0xf3, rdx, dst, src); }
void blsmskq(Register dst, const Operand& src) { bmi1q(0xf3, rdx, dst, src); }
void blsmskq(Register dst, Operand src) { bmi1q(0xf3, rdx, dst, src); }
void blsmskl(Register dst, Register src) { bmi1l(0xf3, rdx, dst, src); }
void blsmskl(Register dst, const Operand& src) { bmi1l(0xf3, rdx, dst, src); }
void blsmskl(Register dst, Operand src) { bmi1l(0xf3, rdx, dst, src); }
void blsrq(Register dst, Register src) { bmi1q(0xf3, rcx, dst, src); }
void blsrq(Register dst, const Operand& src) { bmi1q(0xf3, rcx, dst, src); }
void blsrq(Register dst, Operand src) { bmi1q(0xf3, rcx, dst, src); }
void blsrl(Register dst, Register src) { bmi1l(0xf3, rcx, dst, src); }
void blsrl(Register dst, const Operand& src) { bmi1l(0xf3, rcx, dst, src); }
void blsrl(Register dst, Operand src) { bmi1l(0xf3, rcx, dst, src); }
void tzcntq(Register dst, Register src);
void tzcntq(Register dst, const Operand& src);
void tzcntq(Register dst, Operand src);
void tzcntl(Register dst, Register src);
void tzcntl(Register dst, const Operand& src);
void tzcntl(Register dst, Operand src);
void lzcntq(Register dst, Register src);
void lzcntq(Register dst, const Operand& src);
void lzcntq(Register dst, Operand src);
void lzcntl(Register dst, Register src);
void lzcntl(Register dst, const Operand& src);
void lzcntl(Register dst, Operand src);
void popcntq(Register dst, Register src);
void popcntq(Register dst, const Operand& src);
void popcntq(Register dst, Operand src);
void popcntl(Register dst, Register src);
void popcntl(Register dst, const Operand& src);
void popcntl(Register dst, Operand src);
void bzhiq(Register dst, Register src1, Register src2) {
bmi2q(kNone, 0xf5, dst, src2, src1);
}
void bzhiq(Register dst, const Operand& src1, Register src2) {
void bzhiq(Register dst, Operand src1, Register src2) {
bmi2q(kNone, 0xf5, dst, src2, src1);
}
void bzhil(Register dst, Register src1, Register src2) {
bmi2l(kNone, 0xf5, dst, src2, src1);
}
void bzhil(Register dst, const Operand& src1, Register src2) {
void bzhil(Register dst, Operand src1, Register src2) {
bmi2l(kNone, 0xf5, dst, src2, src1);
}
void mulxq(Register dst1, Register dst2, Register src) {
bmi2q(kF2, 0xf6, dst1, dst2, src);
}
void mulxq(Register dst1, Register dst2, const Operand& src) {
void mulxq(Register dst1, Register dst2, Operand src) {
bmi2q(kF2, 0xf6, dst1, dst2, src);
}
void mulxl(Register dst1, Register dst2, Register src) {
bmi2l(kF2, 0xf6, dst1, dst2, src);
}
void mulxl(Register dst1, Register dst2, const Operand& src) {
void mulxl(Register dst1, Register dst2, Operand src) {
bmi2l(kF2, 0xf6, dst1, dst2, src);
}
void pdepq(Register dst, Register src1, Register src2) {
bmi2q(kF2, 0xf5, dst, src1, src2);
}
void pdepq(Register dst, Register src1, const Operand& src2) {
void pdepq(Register dst, Register src1, Operand src2) {
bmi2q(kF2, 0xf5, dst, src1, src2);
}
void pdepl(Register dst, Register src1, Register src2) {
bmi2l(kF2, 0xf5, dst, src1, src2);
}
void pdepl(Register dst, Register src1, const Operand& src2) {
void pdepl(Register dst, Register src1, Operand src2) {
bmi2l(kF2, 0xf5, dst, src1, src2);
}
void pextq(Register dst, Register src1, Register src2) {
bmi2q(kF3, 0xf5, dst, src1, src2);
}
void pextq(Register dst, Register src1, const Operand& src2) {
void pextq(Register dst, Register src1, Operand src2) {
bmi2q(kF3, 0xf5, dst, src1, src2);
}
void pextl(Register dst, Register src1, Register src2) {
bmi2l(kF3, 0xf5, dst, src1, src2);
}
void pextl(Register dst, Register src1, const Operand& src2) {
void pextl(Register dst, Register src1, Operand src2) {
bmi2l(kF3, 0xf5, dst, src1, src2);
}
void sarxq(Register dst, Register src1, Register src2) {
bmi2q(kF3, 0xf7, dst, src2, src1);
}
void sarxq(Register dst, const Operand& src1, Register src2) {
void sarxq(Register dst, Operand src1, Register src2) {
bmi2q(kF3, 0xf7, dst, src2, src1);
}
void sarxl(Register dst, Register src1, Register src2) {
bmi2l(kF3, 0xf7, dst, src2, src1);
}
void sarxl(Register dst, const Operand& src1, Register src2) {
void sarxl(Register dst, Operand src1, Register src2) {
bmi2l(kF3, 0xf7, dst, src2, src1);
}
void shlxq(Register dst, Register src1, Register src2) {
bmi2q(k66, 0xf7, dst, src2, src1);
}
void shlxq(Register dst, const Operand& src1, Register src2) {
void shlxq(Register dst, Operand src1, Register src2) {
bmi2q(k66, 0xf7, dst, src2, src1);
}
void shlxl(Register dst, Register src1, Register src2) {
bmi2l(k66, 0xf7, dst, src2, src1);
}
void shlxl(Register dst, const Operand& src1, Register src2) {
void shlxl(Register dst, Operand src1, Register src2) {
bmi2l(k66, 0xf7, dst, src2, src1);
}
void shrxq(Register dst, Register src1, Register src2) {
bmi2q(kF2, 0xf7, dst, src2, src1);
}
void shrxq(Register dst, const Operand& src1, Register src2) {
void shrxq(Register dst, Operand src1, Register src2) {
bmi2q(kF2, 0xf7, dst, src2, src1);
}
void shrxl(Register dst, Register src1, Register src2) {
bmi2l(kF2, 0xf7, dst, src2, src1);
}
void shrxl(Register dst, const Operand& src1, Register src2) {
void shrxl(Register dst, Operand src1, Register src2) {
bmi2l(kF2, 0xf7, dst, src2, src1);
}
void rorxq(Register dst, Register src, byte imm8);
void rorxq(Register dst, const Operand& src, byte imm8);
void rorxq(Register dst, Operand src, byte imm8);
void rorxl(Register dst, Register src, byte imm8);
void rorxl(Register dst, const Operand& src, byte imm8);
void rorxl(Register dst, Operand src, byte imm8);
void lfence();
void pause();
......@@ -1952,7 +1923,7 @@ class Assembler : public AssemblerBase {
protected:
// Call near indirect
void call(const Operand& operand);
void call(Operand operand);
private:
byte* addr_at(int pos) { return buffer_ + pos; }
......@@ -1988,8 +1959,8 @@ class Assembler : public AssemblerBase {
// The high bit of reg is used for REX.R, the high bit of op's base
// register is used for REX.B, and the high bit of op's index register
// is used for REX.X. REX.W is set.
inline void emit_rex_64(Register reg, const Operand& op);
inline void emit_rex_64(XMMRegister reg, const Operand& op);
inline void emit_rex_64(Register reg, Operand op);
inline void emit_rex_64(XMMRegister reg, Operand op);
// Emits a REX prefix that encodes a 64-bit operand size and
// the top bit of the register code.
......@@ -2002,7 +1973,7 @@ class Assembler : public AssemblerBase {
// The high bit of op's base register is used for REX.B, and the high
// bit of op's index register is used for REX.X.
// REX.W is set and REX.R clear.
inline void emit_rex_64(const Operand& op);
inline void emit_rex_64(Operand op);
// Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
void emit_rex_64() { emit(0x48); }
......@@ -2014,7 +1985,7 @@ class Assembler : public AssemblerBase {
// The high bit of reg is used for REX.R, the high bit of op's base
// register is used for REX.B, and the high bit of op's index register
// is used for REX.X. REX.W is cleared.
inline void emit_rex_32(Register reg, const Operand& op);
inline void emit_rex_32(Register reg, Operand op);
// High bit of rm_reg goes to REX.B.
// REX.W, REX.R and REX.X are clear.
......@@ -2022,7 +1993,7 @@ class Assembler : public AssemblerBase {
// High bit of base goes to REX.B and high bit of index to REX.X.
// REX.W and REX.R are clear.
inline void emit_rex_32(const Operand& op);
inline void emit_rex_32(Operand op);
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
// REX.W is cleared. If no REX bits are set, no byte is emitted.
......@@ -2032,7 +2003,7 @@ class Assembler : public AssemblerBase {
// register is used for REX.B, and the high bit of op's index register
// is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
// is emitted.
inline void emit_optional_rex_32(Register reg, const Operand& op);
inline void emit_optional_rex_32(Register reg, Operand op);
// As for emit_optional_rex_32(Register, Register), except that
// the registers are XMM registers.
......@@ -2046,18 +2017,18 @@ class Assembler : public AssemblerBase {
// one of the registers is an XMM registers.
inline void emit_optional_rex_32(Register reg, XMMRegister base);
// As for emit_optional_rex_32(Register, const Operand&), except that
// As for emit_optional_rex_32(Register, Operand), except that
// the register is an XMM register.
inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
inline void emit_optional_rex_32(XMMRegister reg, Operand op);
// Optionally do as emit_rex_32(Register) if the register number has
// the high bit set.
inline void emit_optional_rex_32(Register rm_reg);
inline void emit_optional_rex_32(XMMRegister rm_reg);
// Optionally do as emit_rex_32(const Operand&) if the operand register
// Optionally do as emit_rex_32(Operand) if the operand register
// numbers have a high bit set.
inline void emit_optional_rex_32(const Operand& op);
inline void emit_optional_rex_32(Operand op);
void emit_rex(int size) {
if (size == kInt64Size) {
......@@ -2093,8 +2064,7 @@ class Assembler : public AssemblerBase {
SIMDPrefix pp);
void emit_vex3_byte0() { emit(0xc4); }
inline void emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m);
inline void emit_vex3_byte1(XMMRegister reg, const Operand& rm,
LeadingOpcode m);
inline void emit_vex3_byte1(XMMRegister reg, Operand rm, LeadingOpcode m);
inline void emit_vex3_byte2(VexW w, XMMRegister v, VectorLength l,
SIMDPrefix pp);
inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, XMMRegister rm,
......@@ -2103,10 +2073,10 @@ class Assembler : public AssemblerBase {
inline void emit_vex_prefix(Register reg, Register v, Register rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, const Operand& rm,
inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, Operand rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
inline void emit_vex_prefix(Register reg, Register v, const Operand& rm,
inline void emit_vex_prefix(Register reg, Register v, Operand rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
......@@ -2114,14 +2084,14 @@ class Assembler : public AssemblerBase {
// 1- or 4-byte offset for a memory operand. Also encodes
// the second operand of the operation, a register or operation
// subcode, into the reg field of the ModR/M byte.
void emit_operand(Register reg, const Operand& adr) {
void emit_operand(Register reg, Operand adr) {
emit_operand(reg.low_bits(), adr);
}
// Emit the ModR/M byte, and optionally the SIB byte and
// 1- or 4-byte offset for a memory operand. Also used to encode
// a three-bit opcode extension into the ModR/M byte.
void emit_operand(int rm, const Operand& adr);
void emit_operand(int rm, Operand adr);
// Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
void emit_modrm(Register reg, Register rm_reg) {
......@@ -2140,8 +2110,8 @@ class Assembler : public AssemblerBase {
// The first argument is the reg field, the second argument is the r/m field.
void emit_sse_operand(XMMRegister dst, XMMRegister src);
void emit_sse_operand(XMMRegister reg, const Operand& adr);
void emit_sse_operand(Register reg, const Operand& adr);
void emit_sse_operand(XMMRegister reg, Operand adr);
void emit_sse_operand(Register reg, Operand adr);
void emit_sse_operand(XMMRegister dst, Register src);
void emit_sse_operand(Register dst, XMMRegister src);
void emit_sse_operand(XMMRegister dst);
......@@ -2151,37 +2121,28 @@ class Assembler : public AssemblerBase {
// similar, differing just in the opcode or in the reg field of the
// ModR/M byte.
void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
void arithmetic_op_8(byte opcode, Register reg, const Operand& rm_reg);
void arithmetic_op_8(byte opcode, Register reg, Operand rm_reg);
void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
void arithmetic_op_16(byte opcode, Register reg, Operand rm_reg);
// Operate on operands/registers with pointer size, 32-bit or 64-bit size.
void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
void arithmetic_op(byte opcode,
Register reg,
const Operand& rm_reg,
int size);
void arithmetic_op(byte opcode, Register reg, Operand rm_reg, int size);
// Operate on a byte in memory or register.
void immediate_arithmetic_op_8(byte subcode,
Register dst,
Immediate src);
void immediate_arithmetic_op_8(byte subcode,
const Operand& dst,
Immediate src);
void immediate_arithmetic_op_8(byte subcode, Operand dst, Immediate src);
// Operate on a word in memory or register.
void immediate_arithmetic_op_16(byte subcode,
Register dst,
Immediate src);
void immediate_arithmetic_op_16(byte subcode,
const Operand& dst,
Immediate src);
void immediate_arithmetic_op_16(byte subcode, Operand dst, Immediate src);
// Operate on operands/registers with pointer size, 32-bit or 64-bit size.
void immediate_arithmetic_op(byte subcode,
Register dst,
Immediate src,
int size);
void immediate_arithmetic_op(byte subcode,
const Operand& dst,
Immediate src,
void immediate_arithmetic_op(byte subcode, Operand dst, Immediate src,
int size);
// Emit machine code for a shift operation.
......@@ -2209,15 +2170,15 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op(0x0, dst, src, size);
}
void emit_add(Register dst, const Operand& src, int size) {
void emit_add(Register dst, Operand src, int size) {
arithmetic_op(0x03, dst, src, size);
}
void emit_add(const Operand& dst, Register src, int size) {
void emit_add(Operand dst, Register src, int size) {
arithmetic_op(0x1, src, dst, size);
}
void emit_add(const Operand& dst, Immediate src, int size) {
void emit_add(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x0, dst, src, size);
}
......@@ -2225,11 +2186,11 @@ class Assembler : public AssemblerBase {
arithmetic_op(0x23, dst, src, size);
}
void emit_and(Register dst, const Operand& src, int size) {
void emit_and(Register dst, Operand src, int size) {
arithmetic_op(0x23, dst, src, size);
}
void emit_and(const Operand& dst, Register src, int size) {
void emit_and(Operand dst, Register src, int size) {
arithmetic_op(0x21, src, dst, size);
}
......@@ -2237,7 +2198,7 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op(0x4, dst, src, size);
}
void emit_and(const Operand& dst, Immediate src, int size) {
void emit_and(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x4, dst, src, size);
}
......@@ -2245,11 +2206,11 @@ class Assembler : public AssemblerBase {
arithmetic_op(0x3B, dst, src, size);
}
void emit_cmp(Register dst, const Operand& src, int size) {
void emit_cmp(Register dst, Operand src, int size) {
arithmetic_op(0x3B, dst, src, size);
}
void emit_cmp(const Operand& dst, Register src, int size) {
void emit_cmp(Operand dst, Register src, int size) {
arithmetic_op(0x39, src, dst, size);
}
......@@ -2257,17 +2218,17 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op(0x7, dst, src, size);
}
void emit_cmp(const Operand& dst, Immediate src, int size) {
void emit_cmp(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x7, dst, src, size);
}
// Compare {al,ax,eax,rax} with src. If equal, set ZF and write dst into
// src. Otherwise clear ZF and write src into {al,ax,eax,rax}. This
// operation is only atomic if prefixed by the lock instruction.
void emit_cmpxchg(const Operand& dst, Register src, int size);
void emit_cmpxchg(Operand dst, Register src, int size);
void emit_dec(Register dst, int size);
void emit_dec(const Operand& dst, int size);
void emit_dec(Operand dst, int size);
// Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
// Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
......@@ -2278,43 +2239,43 @@ class Assembler : public AssemblerBase {
// Signed multiply instructions.
// rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
void emit_imul(Register src, int size);
void emit_imul(const Operand& src, int size);
void emit_imul(Operand src, int size);
void emit_imul(Register dst, Register src, int size);
void emit_imul(Register dst, const Operand& src, int size);
void emit_imul(Register dst, Operand src, int size);
void emit_imul(Register dst, Register src, Immediate imm, int size);
void emit_imul(Register dst, const Operand& src, Immediate imm, int size);
void emit_imul(Register dst, Operand src, Immediate imm, int size);
void emit_inc(Register dst, int size);
void emit_inc(const Operand& dst, int size);
void emit_inc(Operand dst, int size);
void emit_lea(Register dst, const Operand& src, int size);
void emit_lea(Register dst, Operand src, int size);
void emit_mov(Register dst, const Operand& src, int size);
void emit_mov(Register dst, Operand src, int size);
void emit_mov(Register dst, Register src, int size);
void emit_mov(const Operand& dst, Register src, int size);
void emit_mov(Operand dst, Register src, int size);
void emit_mov(Register dst, Immediate value, int size);
void emit_mov(const Operand& dst, Immediate value, int size);
void emit_mov(Operand dst, Immediate value, int size);
void emit_movzxb(Register dst, const Operand& src, int size);
void emit_movzxb(Register dst, Operand src, int size);
void emit_movzxb(Register dst, Register src, int size);
void emit_movzxw(Register dst, const Operand& src, int size);
void emit_movzxw(Register dst, Operand src, int size);
void emit_movzxw(Register dst, Register src, int size);
void emit_neg(Register dst, int size);
void emit_neg(const Operand& dst, int size);
void emit_neg(Operand dst, int size);
void emit_not(Register dst, int size);
void emit_not(const Operand& dst, int size);
void emit_not(Operand dst, int size);
void emit_or(Register dst, Register src, int size) {
arithmetic_op(0x0B, dst, src, size);
}
void emit_or(Register dst, const Operand& src, int size) {
void emit_or(Register dst, Operand src, int size) {
arithmetic_op(0x0B, dst, src, size);
}
void emit_or(const Operand& dst, Register src, int size) {
void emit_or(Operand dst, Register src, int size) {
arithmetic_op(0x9, src, dst, size);
}
......@@ -2322,7 +2283,7 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op(0x1, dst, src, size);
}
void emit_or(const Operand& dst, Immediate src, int size) {
void emit_or(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x1, dst, src, size);
}
......@@ -2340,28 +2301,28 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op(0x5, dst, src, size);
}
void emit_sub(Register dst, const Operand& src, int size) {
void emit_sub(Register dst, Operand src, int size) {
arithmetic_op(0x2B, dst, src, size);
}
void emit_sub(const Operand& dst, Register src, int size) {
void emit_sub(Operand dst, Register src, int size) {
arithmetic_op(0x29, src, dst, size);
}
void emit_sub(const Operand& dst, Immediate src, int size) {
void emit_sub(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x5, dst, src, size);
}
void emit_test(Register dst, Register src, int size);
void emit_test(Register reg, Immediate mask, int size);
void emit_test(const Operand& op, Register reg, int size);
void emit_test(const Operand& op, Immediate mask, int size);
void emit_test(Register reg, const Operand& op, int size) {
void emit_test(Operand op, Register reg, int size);
void emit_test(Operand op, Immediate mask, int size);
void emit_test(Register reg, Operand op, int size) {
return emit_test(op, reg, size);
}
void emit_xchg(Register dst, Register src, int size);
void emit_xchg(Register dst, const Operand& src, int size);
void emit_xchg(Register dst, Operand src, int size);
void emit_xor(Register dst, Register src, int size) {
if (size == kInt64Size && dst.code() == src.code()) {
......@@ -2373,7 +2334,7 @@ class Assembler : public AssemblerBase {
}
}
void emit_xor(Register dst, const Operand& src, int size) {
void emit_xor(Register dst, Operand src, int size) {
arithmetic_op(0x33, dst, src, size);
}
......@@ -2381,25 +2342,23 @@ class Assembler : public AssemblerBase {
immediate_arithmetic_op(0x6, dst, src, size);
}
void emit_xor(const Operand& dst, Immediate src, int size) {
void emit_xor(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x6, dst, src, size);
}
void emit_xor(const Operand& dst, Register src, int size) {
void emit_xor(Operand dst, Register src, int size) {
arithmetic_op(0x31, src, dst, size);
}
// Most BMI instructions are similar.
void bmi1q(byte op, Register reg, Register vreg, Register rm);
void bmi1q(byte op, Register reg, Register vreg, const Operand& rm);
void bmi1q(byte op, Register reg, Register vreg, Operand rm);
void bmi1l(byte op, Register reg, Register vreg, Register rm);
void bmi1l(byte op, Register reg, Register vreg, const Operand& rm);
void bmi1l(byte op, Register reg, Register vreg, Operand rm);
void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm);
void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg,
const Operand& rm);
void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm);
void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg,
const Operand& rm);
void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
// record the position of jmp/jcc instruction
void record_farjmp_position(Label* L, int pos);
......
src/x64/macro-assembler-x64.cc
View file @ 0237747a
......@@ -214,8 +214,7 @@ void TurboAssembler::CompareRoot(Register with, Heap::RootListIndex index) {
(index << kPointerSizeLog2) - kRootRegisterBias));
}
void TurboAssembler::CompareRoot(const Operand& with,
Heap::RootListIndex index) {
void TurboAssembler::CompareRoot(Operand with, Heap::RootListIndex index) {
DCHECK(root_array_available_);
DCHECK(!with.AddressUsesRegister(kScratchRegister));
LoadRoot(kScratchRegister, index);
......@@ -614,7 +613,7 @@ void TurboAssembler::Cvtss2sd(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Cvtss2sd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtss2sd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvtss2sd(dst, dst, src);
......@@ -632,7 +631,7 @@ void TurboAssembler::Cvtsd2ss(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Cvtsd2ss(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtsd2ss(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvtsd2ss(dst, dst, src);
......@@ -652,7 +651,7 @@ void TurboAssembler::Cvtlsi2sd(XMMRegister dst, Register src) {
}
}
void TurboAssembler::Cvtlsi2sd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtlsi2sd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorpd(dst, dst, dst);
......@@ -674,7 +673,7 @@ void TurboAssembler::Cvtlsi2ss(XMMRegister dst, Register src) {
}
}
void TurboAssembler::Cvtlsi2ss(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtlsi2ss(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorps(dst, dst, dst);
......@@ -696,7 +695,7 @@ void TurboAssembler::Cvtqsi2ss(XMMRegister dst, Register src) {
}
}
void TurboAssembler::Cvtqsi2ss(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtqsi2ss(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorps(dst, dst, dst);
......@@ -718,7 +717,7 @@ void TurboAssembler::Cvtqsi2sd(XMMRegister dst, Register src) {
}
}
void TurboAssembler::Cvtqsi2sd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtqsi2sd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorpd(dst, dst, dst);
......@@ -773,7 +772,7 @@ void TurboAssembler::Cvttss2si(Register dst, XMMRegister src) {
}
}
void TurboAssembler::Cvttss2si(Register dst, const Operand& src) {
void TurboAssembler::Cvttss2si(Register dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvttss2si(dst, src);
......@@ -791,7 +790,7 @@ void TurboAssembler::Cvttsd2si(Register dst, XMMRegister src) {
}
}
void TurboAssembler::Cvttsd2si(Register dst, const Operand& src) {
void TurboAssembler::Cvttsd2si(Register dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvttsd2si(dst, src);
......@@ -809,7 +808,7 @@ void TurboAssembler::Cvttss2siq(Register dst, XMMRegister src) {
}
}
void TurboAssembler::Cvttss2siq(Register dst, const Operand& src) {
void TurboAssembler::Cvttss2siq(Register dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvttss2siq(dst, src);
......@@ -827,7 +826,7 @@ void TurboAssembler::Cvttsd2siq(Register dst, XMMRegister src) {
}
}
void TurboAssembler::Cvttsd2siq(Register dst, const Operand& src) {
void TurboAssembler::Cvttsd2siq(Register dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvttsd2siq(dst, src);
......@@ -836,8 +835,7 @@ void TurboAssembler::Cvttsd2siq(Register dst, const Operand& src) {
}
}
void MacroAssembler::Load(Register dst, const Operand& src, Representation r) {
void MacroAssembler::Load(Register dst, Operand src, Representation r) {
DCHECK(!r.IsDouble());
if (r.IsInteger8()) {
movsxbq(dst, src);
......@@ -854,8 +852,7 @@ void MacroAssembler::Load(Register dst, const Operand& src, Representation r) {
}
}
void MacroAssembler::Store(const Operand& dst, Register src, Representation r) {
void MacroAssembler::Store(Operand dst, Register src, Representation r) {
DCHECK(!r.IsDouble());
if (r.IsInteger8() || r.IsUInteger8()) {
movb(dst, src);
......@@ -885,7 +882,7 @@ void TurboAssembler::Set(Register dst, int64_t x) {
}
}
void TurboAssembler::Set(const Operand& dst, intptr_t x) {
void TurboAssembler::Set(Operand dst, intptr_t x) {
if (kPointerSize == kInt64Size) {
if (is_int32(x)) {
movp(dst, Immediate(static_cast<int32_t>(x)));
......@@ -945,7 +942,7 @@ void TurboAssembler::SmiToInteger32(Register dst, Register src) {
}
}
void TurboAssembler::SmiToInteger32(Register dst, const Operand& src) {
void TurboAssembler::SmiToInteger32(Register dst, Operand src) {
if (SmiValuesAre32Bits()) {
movl(dst, Operand(src, kSmiShift / kBitsPerByte));
} else {
......@@ -991,22 +988,19 @@ void MacroAssembler::Cmp(Register dst, Smi* src) {
}
}
void MacroAssembler::SmiCompare(Register dst, const Operand& src) {
void MacroAssembler::SmiCompare(Register dst, Operand src) {
AssertSmi(dst);
AssertSmi(src);
cmpp(dst, src);
}
void MacroAssembler::SmiCompare(const Operand& dst, Register src) {
void MacroAssembler::SmiCompare(Operand dst, Register src) {
AssertSmi(dst);
AssertSmi(src);
cmpp(dst, src);
}
void MacroAssembler::SmiCompare(const Operand& dst, Smi* src) {
void MacroAssembler::SmiCompare(Operand dst, Smi* src) {
AssertSmi(dst);
if (SmiValuesAre32Bits()) {
cmpl(Operand(dst, kSmiShift / kBitsPerByte), Immediate(src->value()));
......@@ -1016,8 +1010,7 @@ void MacroAssembler::SmiCompare(const Operand& dst, Smi* src) {
}
}
void MacroAssembler::Cmp(const Operand& dst, Smi* src) {
void MacroAssembler::Cmp(Operand dst, Smi* src) {
// The Operand cannot use the smi register.
Register smi_reg = GetSmiConstant(src);
DCHECK(!dst.AddressUsesRegister(smi_reg));
......@@ -1031,7 +1024,7 @@ Condition TurboAssembler::CheckSmi(Register src) {
return zero;
}
Condition TurboAssembler::CheckSmi(const Operand& src) {
Condition TurboAssembler::CheckSmi(Operand src) {
STATIC_ASSERT(kSmiTag == 0);
testb(src, Immediate(kSmiTagMask));
return zero;
......@@ -1057,7 +1050,7 @@ void MacroAssembler::JumpIfNotSmi(Operand src, Label* on_not_smi,
j(NegateCondition(smi), on_not_smi, near_jump);
}
void MacroAssembler::SmiAddConstant(const Operand& dst, Smi* constant) {
void MacroAssembler::SmiAddConstant(Operand dst, Smi* constant) {
if (constant->value() != 0) {
if (SmiValuesAre32Bits()) {
addl(Operand(dst, kSmiShift / kBitsPerByte),
......@@ -1200,7 +1193,7 @@ void TurboAssembler::Movups(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Movups(XMMRegister dst, const Operand& src) {
void TurboAssembler::Movups(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovups(dst, src);
......@@ -1209,7 +1202,7 @@ void TurboAssembler::Movups(XMMRegister dst, const Operand& src) {
}
}
void TurboAssembler::Movups(const Operand& dst, XMMRegister src) {
void TurboAssembler::Movups(Operand dst, XMMRegister src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovups(dst, src);
......@@ -1236,7 +1229,7 @@ void TurboAssembler::Movsd(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Movsd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Movsd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovsd(dst, src);
......@@ -1245,7 +1238,7 @@ void TurboAssembler::Movsd(XMMRegister dst, const Operand& src) {
}
}
void TurboAssembler::Movsd(const Operand& dst, XMMRegister src) {
void TurboAssembler::Movsd(Operand dst, XMMRegister src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovsd(dst, src);
......@@ -1263,7 +1256,7 @@ void TurboAssembler::Movss(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Movss(XMMRegister dst, const Operand& src) {
void TurboAssembler::Movss(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovss(dst, src);
......@@ -1272,7 +1265,7 @@ void TurboAssembler::Movss(XMMRegister dst, const Operand& src) {
}
}
void TurboAssembler::Movss(const Operand& dst, XMMRegister src) {
void TurboAssembler::Movss(Operand dst, XMMRegister src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovss(dst, src);
......@@ -1290,7 +1283,7 @@ void TurboAssembler::Movd(XMMRegister dst, Register src) {
}
}
void TurboAssembler::Movd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Movd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vmovd(dst, src);
......@@ -1353,7 +1346,7 @@ void TurboAssembler::Xorps(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Xorps(XMMRegister dst, const Operand& src) {
void TurboAssembler::Xorps(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorps(dst, dst, src);
......@@ -1391,7 +1384,7 @@ void TurboAssembler::Sqrtsd(XMMRegister dst, XMMRegister src) {
}
}
void TurboAssembler::Sqrtsd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Sqrtsd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vsqrtsd(dst, dst, src);
......@@ -1409,7 +1402,7 @@ void TurboAssembler::Ucomiss(XMMRegister src1, XMMRegister src2) {
}
}
void TurboAssembler::Ucomiss(XMMRegister src1, const Operand& src2) {
void TurboAssembler::Ucomiss(XMMRegister src1, Operand src2) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vucomiss(src1, src2);
......@@ -1427,7 +1420,7 @@ void TurboAssembler::Ucomisd(XMMRegister src1, XMMRegister src2) {
}
}
void TurboAssembler::Ucomisd(XMMRegister src1, const Operand& src2) {
void TurboAssembler::Ucomisd(XMMRegister src1, Operand src2) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vucomisd(src1, src2);
......@@ -1468,8 +1461,7 @@ void MacroAssembler::Cmp(Register dst, Handle<Object> source) {
}
}
void MacroAssembler::Cmp(const Operand& dst, Handle<Object> source) {
void MacroAssembler::Cmp(Operand dst, Handle<Object> source) {
AllowDeferredHandleDereference smi_check;
if (source->IsSmi()) {
Cmp(dst, Smi::cast(*source));
......@@ -1489,7 +1481,7 @@ void TurboAssembler::Move(Register result, Handle<HeapObject> object,
movp(result, reinterpret_cast<void*>(object.address()), rmode);
}
void TurboAssembler::Move(const Operand& dst, Handle<HeapObject> object,
void TurboAssembler::Move(Operand dst, Handle<HeapObject> object,
RelocInfo::Mode rmode) {
Move(kScratchRegister, object, rmode);
movp(dst, kScratchRegister);
......@@ -1526,7 +1518,7 @@ void TurboAssembler::Push(Register src) {
}
}
void TurboAssembler::Push(const Operand& src) {
void TurboAssembler::Push(Operand src) {
if (kPointerSize == kInt64Size) {
pushq(src);
} else {
......@@ -1536,8 +1528,7 @@ void TurboAssembler::Push(const Operand& src) {
}
}
void MacroAssembler::PushQuad(const Operand& src) {
void MacroAssembler::PushQuad(Operand src) {
if (kPointerSize == kInt64Size) {
pushq(src);
} else {
......@@ -1577,8 +1568,7 @@ void MacroAssembler::Pop(Register dst) {
}
}
void MacroAssembler::Pop(const Operand& dst) {
void MacroAssembler::Pop(Operand dst) {
if (kPointerSize == kInt64Size) {
popq(dst);
} else {
......@@ -1594,8 +1584,7 @@ void MacroAssembler::Pop(const Operand& dst) {
}
}
void MacroAssembler::PopQuad(const Operand& dst) {
void MacroAssembler::PopQuad(Operand dst) {
if (kPointerSize == kInt64Size) {
popq(dst);
} else {
......@@ -1610,8 +1599,7 @@ void MacroAssembler::Jump(ExternalReference ext) {
jmp(kScratchRegister);
}
void MacroAssembler::Jump(const Operand& op) {
void MacroAssembler::Jump(Operand op) {
if (kPointerSize == kInt64Size) {
jmp(op);
} else {
......@@ -1653,7 +1641,7 @@ void TurboAssembler::Call(ExternalReference ext) {
DCHECK_EQ(end_position, pc_offset());
}
void TurboAssembler::Call(const Operand& op) {
void TurboAssembler::Call(Operand op) {
if (kPointerSize == kInt64Size && !CpuFeatures::IsSupported(ATOM)) {
call(op);
} else {
......@@ -1755,7 +1743,7 @@ void TurboAssembler::Pinsrd(XMMRegister dst, Register src, int8_t imm8) {
}
}
void TurboAssembler::Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8) {
void TurboAssembler::Pinsrd(XMMRegister dst, Operand src, int8_t imm8) {
DCHECK(imm8 == 0 || imm8 == 1);
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope sse_scope(this, SSE4_1);
......@@ -1785,7 +1773,7 @@ void TurboAssembler::Lzcntl(Register dst, Register src) {
xorl(dst, Immediate(31)); // for x in [0..31], 31^x == 31 - x
}
void TurboAssembler::Lzcntl(Register dst, const Operand& src) {
void TurboAssembler::Lzcntl(Register dst, Operand src) {
if (CpuFeatures::IsSupported(LZCNT)) {
CpuFeatureScope scope(this, LZCNT);
lzcntl(dst, src);
......@@ -1813,7 +1801,7 @@ void TurboAssembler::Lzcntq(Register dst, Register src) {
xorl(dst, Immediate(63)); // for x in [0..63], 63^x == 63 - x
}
void TurboAssembler::Lzcntq(Register dst, const Operand& src) {
void TurboAssembler::Lzcntq(Register dst, Operand src) {
if (CpuFeatures::IsSupported(LZCNT)) {
CpuFeatureScope scope(this, LZCNT);
lzcntq(dst, src);
......@@ -1841,7 +1829,7 @@ void TurboAssembler::Tzcntq(Register dst, Register src) {
bind(&not_zero_src);
}
void TurboAssembler::Tzcntq(Register dst, const Operand& src) {
void TurboAssembler::Tzcntq(Register dst, Operand src) {
if (CpuFeatures::IsSupported(BMI1)) {
CpuFeatureScope scope(this, BMI1);
tzcntq(dst, src);
......@@ -1868,7 +1856,7 @@ void TurboAssembler::Tzcntl(Register dst, Register src) {
bind(&not_zero_src);
}
void TurboAssembler::Tzcntl(Register dst, const Operand& src) {
void TurboAssembler::Tzcntl(Register dst, Operand src) {
if (CpuFeatures::IsSupported(BMI1)) {
CpuFeatureScope scope(this, BMI1);
tzcntl(dst, src);
......@@ -1890,7 +1878,7 @@ void TurboAssembler::Popcntl(Register dst, Register src) {
UNREACHABLE();
}
void TurboAssembler::Popcntl(Register dst, const Operand& src) {
void TurboAssembler::Popcntl(Register dst, Operand src) {
if (CpuFeatures::IsSupported(POPCNT)) {
CpuFeatureScope scope(this, POPCNT);
popcntl(dst, src);
......@@ -1908,7 +1896,7 @@ void TurboAssembler::Popcntq(Register dst, Register src) {
UNREACHABLE();
}
void TurboAssembler::Popcntq(Register dst, const Operand& src) {
void TurboAssembler::Popcntq(Register dst, Operand src) {
if (CpuFeatures::IsSupported(POPCNT)) {
CpuFeatureScope scope(this, POPCNT);
popcntq(dst, src);
......@@ -2064,8 +2052,7 @@ void MacroAssembler::AssertSmi(Register object) {
}
}
void MacroAssembler::AssertSmi(const Operand& object) {
void MacroAssembler::AssertSmi(Operand object) {
if (emit_debug_code()) {
Condition is_smi = CheckSmi(object);
Check(is_smi, AbortReason::kOperandIsNotASmi);
......
src/x64/macro-assembler-x64.h
View file @ 0237747a
......@@ -147,8 +147,7 @@ class TurboAssembler : public Assembler {
}
#define AVX_OP2_X(macro_name, name) \
AVX_OP2_WITH_TYPE(macro_name, name, XMMRegister)
#define AVX_OP2_O(macro_name, name) \
AVX_OP2_WITH_TYPE(macro_name, name, const Operand&)
#define AVX_OP2_O(macro_name, name) AVX_OP2_WITH_TYPE(macro_name, name, Operand)
#define AVX_OP2_XO(macro_name, name) \
AVX_OP2_X(macro_name, name) \
AVX_OP2_O(macro_name, name)
......@@ -167,20 +166,20 @@ class TurboAssembler : public Assembler {
#undef AVX_OP2_WITH_TYPE
void Xorps(XMMRegister dst, XMMRegister src);
void Xorps(XMMRegister dst, const Operand& src);
void Xorps(XMMRegister dst, Operand src);
void Movd(XMMRegister dst, Register src);
void Movd(XMMRegister dst, const Operand& src);
void Movd(XMMRegister dst, Operand src);
void Movd(Register dst, XMMRegister src);
void Movq(XMMRegister dst, Register src);
void Movq(Register dst, XMMRegister src);
void Movsd(XMMRegister dst, XMMRegister src);
void Movsd(XMMRegister dst, const Operand& src);
void Movsd(const Operand& dst, XMMRegister src);
void Movsd(XMMRegister dst, Operand src);
void Movsd(Operand dst, XMMRegister src);
void Movss(XMMRegister dst, XMMRegister src);
void Movss(XMMRegister dst, const Operand& src);
void Movss(const Operand& dst, XMMRegister src);
void Movss(XMMRegister dst, Operand src);
void Movss(Operand dst, XMMRegister src);
void PushReturnAddressFrom(Register src) { pushq(src); }
void PopReturnAddressTo(Register dst) { popq(dst); }
......@@ -193,25 +192,25 @@ class TurboAssembler : public Assembler {
// Load a register with a long value as efficiently as possible.
void Set(Register dst, int64_t x);
void Set(const Operand& dst, intptr_t x);
void Set(Operand dst, intptr_t x);
// Operations on roots in the root-array.
void LoadRoot(Register destination, Heap::RootListIndex index);
void LoadRoot(const Operand& destination, Heap::RootListIndex index) {
void LoadRoot(Operand destination, Heap::RootListIndex index) {
LoadRoot(kScratchRegister, index);
movp(destination, kScratchRegister);
}
void Movups(XMMRegister dst, XMMRegister src);
void Movups(XMMRegister dst, const Operand& src);
void Movups(const Operand& dst, XMMRegister src);
void Movups(XMMRegister dst, Operand src);
void Movups(Operand dst, XMMRegister src);
void Movapd(XMMRegister dst, XMMRegister src);
void Movaps(XMMRegister dst, XMMRegister src);
void Movmskpd(Register dst, XMMRegister src);
void Movmskps(Register dst, XMMRegister src);
void Push(Register src);
void Push(const Operand& src);
void Push(Operand src);
void Push(Immediate value);
void Push(Smi* smi);
void Push(Handle<HeapObject> source);
......@@ -242,23 +241,23 @@ class TurboAssembler : public Assembler {
Label::Distance condition_met_distance = Label::kFar);
void Cvtss2sd(XMMRegister dst, XMMRegister src);
void Cvtss2sd(XMMRegister dst, const Operand& src);
void Cvtss2sd(XMMRegister dst, Operand src);
void Cvtsd2ss(XMMRegister dst, XMMRegister src);
void Cvtsd2ss(XMMRegister dst, const Operand& src);
void Cvtsd2ss(XMMRegister dst, Operand src);
void Cvttsd2si(Register dst, XMMRegister src);
void Cvttsd2si(Register dst, const Operand& src);
void Cvttsd2si(Register dst, Operand src);
void Cvttsd2siq(Register dst, XMMRegister src);
void Cvttsd2siq(Register dst, const Operand& src);
void Cvttsd2siq(Register dst, Operand src);
void Cvttss2si(Register dst, XMMRegister src);
void Cvttss2si(Register dst, const Operand& src);
void Cvttss2si(Register dst, Operand src);
void Cvttss2siq(Register dst, XMMRegister src);
void Cvttss2siq(Register dst, const Operand& src);
void Cvttss2siq(Register dst, Operand src);
void Cvtqsi2ss(XMMRegister dst, Register src);
void Cvtqsi2ss(XMMRegister dst, const Operand& src);
void Cvtqsi2ss(XMMRegister dst, Operand src);
void Cvtqsi2sd(XMMRegister dst, Register src);
void Cvtqsi2sd(XMMRegister dst, const Operand& src);
void Cvtqsi2sd(XMMRegister dst, Operand src);
void Cvtlsi2ss(XMMRegister dst, Register src);
void Cvtlsi2ss(XMMRegister dst, const Operand& src);
void Cvtlsi2ss(XMMRegister dst, Operand src);
void Cvtqui2ss(XMMRegister dst, Register src, Register tmp);
void Cvtqui2sd(XMMRegister dst, Register src, Register tmp);
......@@ -266,35 +265,35 @@ class TurboAssembler : public Assembler {
// hinders register renaming and makes dependence chains longer. So we use
// xorpd to clear the dst register before cvtsi2sd to solve this issue.
void Cvtlsi2sd(XMMRegister dst, Register src);
void Cvtlsi2sd(XMMRegister dst, const Operand& src);
void Cvtlsi2sd(XMMRegister dst, Operand src);
void Roundss(XMMRegister dst, XMMRegister src, RoundingMode mode);
void Roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
void Sqrtsd(XMMRegister dst, XMMRegister src);
void Sqrtsd(XMMRegister dst, const Operand& src);
void Sqrtsd(XMMRegister dst, Operand src);
void Ucomiss(XMMRegister src1, XMMRegister src2);
void Ucomiss(XMMRegister src1, const Operand& src2);
void Ucomiss(XMMRegister src1, Operand src2);
void Ucomisd(XMMRegister src1, XMMRegister src2);
void Ucomisd(XMMRegister src1, const Operand& src2);
void Ucomisd(XMMRegister src1, Operand src2);
void Lzcntq(Register dst, Register src);
void Lzcntq(Register dst, const Operand& src);
void Lzcntq(Register dst, Operand src);
void Lzcntl(Register dst, Register src);
void Lzcntl(Register dst, const Operand& src);
void Lzcntl(Register dst, Operand src);
void Tzcntq(Register dst, Register src);
void Tzcntq(Register dst, const Operand& src);
void Tzcntq(Register dst, Operand src);
void Tzcntl(Register dst, Register src);
void Tzcntl(Register dst, const Operand& src);
void Tzcntl(Register dst, Operand src);
void Popcntl(Register dst, Register src);
void Popcntl(Register dst, const Operand& src);
void Popcntl(Register dst, Operand src);
void Popcntq(Register dst, Register src);
void Popcntq(Register dst, const Operand& src);
void Popcntq(Register dst, Operand src);
// Is the value a tagged smi.
Condition CheckSmi(Register src);
Condition CheckSmi(const Operand& src);
Condition CheckSmi(Operand src);
// Jump to label if the value is a tagged smi.
void JumpIfSmi(Register src, Label* on_smi,
......@@ -302,7 +301,7 @@ class TurboAssembler : public Assembler {
void Move(Register dst, Smi* source);
void Move(const Operand& dst, Smi* source) {
void Move(Operand dst, Smi* source) {
Register constant = GetSmiConstant(source);
movp(dst, constant);
}
......@@ -322,7 +321,7 @@ class TurboAssembler : public Assembler {
void Move(Register dst, Handle<HeapObject> source,
RelocInfo::Mode rmode = RelocInfo::EMBEDDED_OBJECT);
void Move(const Operand& dst, Handle<HeapObject> source,
void Move(Operand dst, Handle<HeapObject> source,
RelocInfo::Mode rmode = RelocInfo::EMBEDDED_OBJECT);
// Loads a pointer into a register with a relocation mode.
......@@ -336,13 +335,13 @@ class TurboAssembler : public Assembler {
// Convert smi to 32-bit integer. I.e., not sign extended into
// high 32 bits of destination.
void SmiToInteger32(Register dst, Register src);
void SmiToInteger32(Register dst, const Operand& src);
void SmiToInteger32(Register dst, Operand src);
// Loads the address of the external reference into the destination
// register.
void LoadAddress(Register destination, ExternalReference source);
void Call(const Operand& op);
void Call(Operand op);
void Call(Handle<Code> code_object, RelocInfo::Mode rmode);
void Call(Address destination, RelocInfo::Mode rmode);
void Call(ExternalReference ext);
......@@ -368,7 +367,7 @@ class TurboAssembler : public Assembler {
// Opcode: REX_opt FF /2 m64
return (target.high_bit() != 0) ? 3 : 2;
}
int CallSize(const Operand& target) {
int CallSize(Operand target) {
// Opcode: REX_opt FF /2 m64
return (target.requires_rex() ? 2 : 1) + target.operand_size();
}
......@@ -380,10 +379,10 @@ class TurboAssembler : public Assembler {
// Non-SSE2 instructions.
void Pextrd(Register dst, XMMRegister src, int8_t imm8);
void Pinsrd(XMMRegister dst, Register src, int8_t imm8);
void Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8);
void Pinsrd(XMMRegister dst, Operand src, int8_t imm8);
void CompareRoot(Register with, Heap::RootListIndex index);
void CompareRoot(const Operand& with, Heap::RootListIndex index);
void CompareRoot(Operand with, Heap::RootListIndex index);
// Generates function and stub prologue code.
void StubPrologue(StackFrame::Type type);
......@@ -560,8 +559,7 @@ class MacroAssembler : public TurboAssembler {
CompareRoot(with, index);
j(equal, if_equal, if_equal_distance);
}
void JumpIfRoot(const Operand& with, Heap::RootListIndex index,
Label* if_equal,
void JumpIfRoot(Operand with, Heap::RootListIndex index, Label* if_equal,
Label::Distance if_equal_distance = Label::kFar) {
CompareRoot(with, index);
j(equal, if_equal, if_equal_distance);
......@@ -574,7 +572,7 @@ class MacroAssembler : public TurboAssembler {
CompareRoot(with, index);
j(not_equal, if_not_equal, if_not_equal_distance);
}
void JumpIfNotRoot(const Operand& with, Heap::RootListIndex index,
void JumpIfNotRoot(Operand with, Heap::RootListIndex index,
Label* if_not_equal,
Label::Distance if_not_equal_distance = Label::kFar) {
CompareRoot(with, index);
......@@ -673,9 +671,9 @@ class MacroAssembler : public TurboAssembler {
// otherwise use Cmp.
void SmiCompare(Register smi1, Register smi2);
void SmiCompare(Register dst, Smi* src);
void SmiCompare(Register dst, const Operand& src);
void SmiCompare(const Operand& dst, Register src);
void SmiCompare(const Operand& dst, Smi* src);
void SmiCompare(Register dst, Operand src);
void SmiCompare(Operand dst, Register src);
void SmiCompare(Operand dst, Smi* src);
// Functions performing a check on a known or potential smi. Returns
// a condition that is satisfied if the check is successful.
......@@ -699,7 +697,7 @@ class MacroAssembler : public TurboAssembler {
// Add an integer constant to a tagged smi, giving a tagged smi as result.
// No overflow testing on the result is done.
void SmiAddConstant(const Operand& dst, Smi* constant);
void SmiAddConstant(Operand dst, Smi* constant);
// Specialized operations
......@@ -717,13 +715,13 @@ class MacroAssembler : public TurboAssembler {
// Macro instructions.
// Load/store with specific representation.
void Load(Register dst, const Operand& src, Representation r);
void Store(const Operand& dst, Register src, Representation r);
void Load(Register dst, Operand src, Representation r);
void Store(Operand dst, Register src, Representation r);
void Cmp(Register dst, Handle<Object> source);
void Cmp(const Operand& dst, Handle<Object> source);
void Cmp(Operand dst, Handle<Object> source);
void Cmp(Register dst, Smi* src);
void Cmp(const Operand& dst, Smi* src);
void Cmp(Operand dst, Smi* src);
// Emit code to discard a non-negative number of pointer-sized elements
// from the stack, clobbering only the rsp register.
......@@ -734,11 +732,11 @@ class MacroAssembler : public TurboAssembler {
void DropUnderReturnAddress(int stack_elements,
Register scratch = kScratchRegister);
void PushQuad(const Operand& src);
void PushQuad(Operand src);
void PushImm32(int32_t imm32);
void Pop(Register dst);
void Pop(const Operand& dst);
void PopQuad(const Operand& dst);
void Pop(Operand dst);
void PopQuad(Operand dst);
#define AVX_OP2_WITH_TYPE(macro_name, name, src_type) \
void macro_name(XMMRegister dst, src_type src) { \
......@@ -751,8 +749,7 @@ class MacroAssembler : public TurboAssembler {
}
#define AVX_OP2_X(macro_name, name) \
AVX_OP2_WITH_TYPE(macro_name, name, XMMRegister)
#define AVX_OP2_O(macro_name, name) \
AVX_OP2_WITH_TYPE(macro_name, name, const Operand&)
#define AVX_OP2_O(macro_name, name) AVX_OP2_WITH_TYPE(macro_name, name, Operand)
#define AVX_OP2_XO(macro_name, name) \
AVX_OP2_X(macro_name, name) \
AVX_OP2_O(macro_name, name)
......@@ -790,7 +787,7 @@ class MacroAssembler : public TurboAssembler {
// Control Flow
void Jump(Address destination, RelocInfo::Mode rmode);
void Jump(ExternalReference ext);
void Jump(const Operand& op);
void Jump(Operand op);
void Jump(Handle<Code> code_object, RelocInfo::Mode rmode);
// Generates a trampoline to jump to the off-heap instruction stream.
......@@ -832,7 +829,7 @@ class MacroAssembler : public TurboAssembler {
// Abort execution if argument is not a smi, enabled via --debug-code.
void AssertSmi(Register object);
void AssertSmi(const Operand& object);
void AssertSmi(Operand object);
// Abort execution if argument is not a FixedArray, enabled via --debug-code.
void AssertFixedArray(Register object);
......
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