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Commit 02253a90 authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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s390: [wasm-simd] Implement simd unary and boolean operations 

Change-Id: I0c85de569b75e47dddb54c2dc4101da252547751
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2023370Reviewed-by: 's avatarJoran Siu <joransiu@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#66011}
parent 62cde006
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Showing with 138 additions and 40 deletions
src/compiler/backend/s390/code-generator-s390.cc
View file @ 02253a90
...@@ -3378,6 +3378,85 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3378,6 +3378,85 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
VECTOR_SHIFT(vesrlv, 0); VECTOR_SHIFT(vesrlv, 0);
break; break;
} }
// vector unary ops
case kS390_F32x4Abs: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(2), Condition(0), Condition(2));
break;
}
case kS390_F32x4Neg: {
__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_I32x4Neg: {
__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
Condition(0), Condition(2));
break;
}
case kS390_I16x8Neg: {
__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
Condition(0), Condition(1));
break;
}
case kS390_I8x16Neg: {
__ vlc(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0),
Condition(0), Condition(0));
break;
}
case kS390_F32x4RecipApprox: {
__ lgfi(kScratchReg, Operand(1));
__ ConvertIntToFloat(kScratchDoubleReg, kScratchReg);
__ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(2));
__ vfd(i.OutputSimd128Register(), kScratchDoubleReg,
i.InputSimd128Register(0), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4RecipSqrtApprox: {
DoubleRegister tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vfsq(tempFPReg1, i.InputSimd128Register(0), Condition(0), Condition(0),
Condition(2));
__ lgfi(kScratchReg, Operand(1));
__ ConvertIntToFloat(kScratchDoubleReg, kScratchReg);
__ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(2));
__ vfd(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_S128Not: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
__ vno(dst, src, src, Condition(0), Condition(0), Condition(0));
break;
}
// vector boolean unops
case kS390_S1x4AnyTrue:
case kS390_S1x8AnyTrue:
case kS390_S1x16AnyTrue: {
Simd128Register src = i.InputSimd128Register(0);
Register dst = i.OutputRegister();
Register temp = i.TempRegister(0);
__ lgfi(dst, Operand(1));
__ xgr(temp, temp);
__ vtm(src, src, Condition(0), Condition(0), Condition(0));
__ locgr(Condition(8), dst, temp);
break;
}
case kS390_S1x4AllTrue:
case kS390_S1x8AllTrue:
case kS390_S1x16AllTrue: {
Simd128Register src = i.InputSimd128Register(0);
Register dst = i.OutputRegister();
Register temp = i.TempRegister(0);
__ lgfi(temp, Operand(1));
__ xgr(dst, dst);
__ vceq(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
Condition(0), Condition(2));
__ vtm(src, kScratchDoubleReg, Condition(0), Condition(0), Condition(0));
__ locgr(Condition(1), dst, temp);
break;
}
// vector bitwise ops // vector bitwise ops
case kS390_S128And: { case kS390_S128And: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
...@@ -3406,12 +3485,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3406,12 +3485,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vx(dst, dst, src, Condition(0), Condition(0), Condition(0)); __ vx(dst, dst, src, Condition(0), Condition(0), Condition(0));
break; break;
} }
case kS390_S128Not: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
__ vno(dst, src, src, Condition(0), Condition(0), Condition(0));
break;
}
case kS390_S128Select: { case kS390_S128Select: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
Simd128Register mask = i.InputSimd128Register(0); Simd128Register mask = i.InputSimd128Register(0);
......
src/compiler/backend/s390/instruction-codes-s390.h
View file @ 02253a90
...@@ -208,6 +208,10 @@ namespace compiler { ...@@ -208,6 +208,10 @@ namespace compiler {
V(S390_F32x4Ne) \ V(S390_F32x4Ne) \
V(S390_F32x4Lt) \ V(S390_F32x4Lt) \
V(S390_F32x4Le) \ V(S390_F32x4Le) \
V(S390_F32x4Abs) \
V(S390_F32x4Neg) \
V(S390_F32x4RecipApprox) \
V(S390_F32x4RecipSqrtApprox) \
V(S390_I32x4Splat) \ V(S390_I32x4Splat) \
V(S390_I32x4ExtractLane) \ V(S390_I32x4ExtractLane) \
V(S390_I32x4ReplaceLane) \ V(S390_I32x4ReplaceLane) \
...@@ -225,6 +229,7 @@ namespace compiler { ...@@ -225,6 +229,7 @@ namespace compiler {
V(S390_I32x4GeS) \ V(S390_I32x4GeS) \
V(S390_I32x4GtU) \ V(S390_I32x4GtU) \
V(S390_I32x4GeU) \ V(S390_I32x4GeU) \
V(S390_I32x4Neg) \
V(S390_I16x8Splat) \ V(S390_I16x8Splat) \
V(S390_I32x4Shl) \ V(S390_I32x4Shl) \
V(S390_I32x4ShrS) \ V(S390_I32x4ShrS) \
...@@ -249,6 +254,7 @@ namespace compiler { ...@@ -249,6 +254,7 @@ namespace compiler {
V(S390_I16x8Shl) \ V(S390_I16x8Shl) \
V(S390_I16x8ShrS) \ V(S390_I16x8ShrS) \
V(S390_I16x8ShrU) \ V(S390_I16x8ShrU) \
V(S390_I16x8Neg) \
V(S390_I8x16Splat) \ V(S390_I8x16Splat) \
V(S390_I8x16ExtractLaneU) \ V(S390_I8x16ExtractLaneU) \
V(S390_I8x16ExtractLaneS) \ V(S390_I8x16ExtractLaneS) \
...@@ -269,6 +275,13 @@ namespace compiler { ...@@ -269,6 +275,13 @@ namespace compiler {
V(S390_I8x16Shl) \ V(S390_I8x16Shl) \
V(S390_I8x16ShrS) \ V(S390_I8x16ShrS) \
V(S390_I8x16ShrU) \ V(S390_I8x16ShrU) \
V(S390_I8x16Neg) \
V(S390_S1x4AnyTrue) \
V(S390_S1x8AnyTrue) \
V(S390_S1x16AnyTrue) \
V(S390_S1x4AllTrue) \
V(S390_S1x8AllTrue) \
V(S390_S1x16AllTrue) \
V(S390_S128And) \ V(S390_S128And) \
V(S390_S128Or) \ V(S390_S128Or) \
V(S390_S128Xor) \ V(S390_S128Xor) \
......
src/compiler/backend/s390/instruction-scheduler-s390.cc
View file @ 02253a90
...@@ -154,6 +154,10 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -154,6 +154,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_F32x4Ne: case kS390_F32x4Ne:
case kS390_F32x4Lt: case kS390_F32x4Lt:
case kS390_F32x4Le: case kS390_F32x4Le:
case kS390_F32x4Abs:
case kS390_F32x4Neg:
case kS390_F32x4RecipApprox:
case kS390_F32x4RecipSqrtApprox:
case kS390_I32x4Splat: case kS390_I32x4Splat:
case kS390_I32x4ExtractLane: case kS390_I32x4ExtractLane:
case kS390_I32x4ReplaceLane: case kS390_I32x4ReplaceLane:
...@@ -174,6 +178,7 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -174,6 +178,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I32x4Shl: case kS390_I32x4Shl:
case kS390_I32x4ShrS: case kS390_I32x4ShrS:
case kS390_I32x4ShrU: case kS390_I32x4ShrU:
case kS390_I32x4Neg:
case kS390_I16x8Splat: case kS390_I16x8Splat:
case kS390_I16x8ExtractLaneU: case kS390_I16x8ExtractLaneU:
case kS390_I16x8ExtractLaneS: case kS390_I16x8ExtractLaneS:
...@@ -195,6 +200,7 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -195,6 +200,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I16x8Shl: case kS390_I16x8Shl:
case kS390_I16x8ShrS: case kS390_I16x8ShrS:
case kS390_I16x8ShrU: case kS390_I16x8ShrU:
case kS390_I16x8Neg:
case kS390_I8x16Splat: case kS390_I8x16Splat:
case kS390_I8x16ExtractLaneU: case kS390_I8x16ExtractLaneU:
case kS390_I8x16ExtractLaneS: case kS390_I8x16ExtractLaneS:
...@@ -215,6 +221,13 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -215,6 +221,13 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I8x16Shl: case kS390_I8x16Shl:
case kS390_I8x16ShrS: case kS390_I8x16ShrS:
case kS390_I8x16ShrU: case kS390_I8x16ShrU:
case kS390_I8x16Neg:
case kS390_S1x4AnyTrue:
case kS390_S1x8AnyTrue:
case kS390_S1x16AnyTrue:
case kS390_S1x4AllTrue:
case kS390_S1x8AllTrue:
case kS390_S1x16AllTrue:
case kS390_S128And: case kS390_S128And:
case kS390_S128Or: case kS390_S128Or:
case kS390_S128Xor: case kS390_S128Xor:
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ 02253a90
...@@ -2571,7 +2571,15 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2571,7 +2571,15 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(S128Or) \ V(S128Or) \
V(S128Xor) V(S128Xor)
#define SIMD_UNOP_LIST(V) V(S128Not) #define SIMD_UNOP_LIST(V) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4RecipApprox) \
V(F32x4RecipSqrtApprox) \
V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg) \
V(S128Not)
#define SIMD_SHIFT_OPCODES(V) \ #define SIMD_SHIFT_OPCODES(V) \
V(I32x4Shl) \ V(I32x4Shl) \
...@@ -2584,6 +2592,14 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { ...@@ -2584,6 +2592,14 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I8x16ShrS) \ V(I8x16ShrS) \
V(I8x16ShrU) V(I8x16ShrU)
#define SIMD_BOOL_LIST(V) \
V(S1x4AnyTrue) \
V(S1x8AnyTrue) \
V(S1x16AnyTrue) \
V(S1x4AllTrue) \
V(S1x8AllTrue) \
V(S1x16AllTrue)
#define SIMD_VISIT_SPLAT(Type) \ #define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \ void InstructionSelector::Visit##Type##Splat(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
...@@ -2632,11 +2648,12 @@ SIMD_BINOP_LIST(SIMD_VISIT_BINOP) ...@@ -2632,11 +2648,12 @@ SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP #undef SIMD_VISIT_BINOP
#undef SIMD_BINOP_LIST #undef SIMD_BINOP_LIST
#define SIMD_VISIT_UNOP(Opcode) \ #define SIMD_VISIT_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \ void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \ S390OperandGenerator g(this); \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \ InstructionOperand temps[] = {g.TempSimd128Register()}; \
g.UseRegister(node->InputAt(0))); \ Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), arraysize(temps), temps); \
} }
SIMD_UNOP_LIST(SIMD_VISIT_UNOP) SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_UNOP #undef SIMD_VISIT_UNOP
...@@ -2652,6 +2669,16 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP) ...@@ -2652,6 +2669,16 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
SIMD_SHIFT_OPCODES(SIMD_VISIT_SHIFT) SIMD_SHIFT_OPCODES(SIMD_VISIT_SHIFT)
#undef SIMD_VISIT_SHIFT #undef SIMD_VISIT_SHIFT
#undef SIMD_SHIFT_OPCODES #undef SIMD_SHIFT_OPCODES
#define SIMD_VISIT_BOOL(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempRegister()}; \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps); \
}
SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
#undef SIMD_VISIT_BOOL
#undef SIMD_TYPES #undef SIMD_TYPES
void InstructionSelector::VisitS128Zero(Node* node) { void InstructionSelector::VisitS128Zero(Node* node) {
...@@ -2666,8 +2693,6 @@ void InstructionSelector::VisitS128Select(Node* node) { ...@@ -2666,8 +2693,6 @@ void InstructionSelector::VisitS128Select(Node* node) {
g.UseRegister(node->InputAt(2))); g.UseRegister(node->InputAt(2)));
} }
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) { void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
...@@ -2684,8 +2709,6 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) { ...@@ -2684,8 +2709,6 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) { void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
...@@ -2694,8 +2717,6 @@ void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) { ...@@ -2694,8 +2717,6 @@ void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) { void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
...@@ -2745,16 +2766,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); } ...@@ -2745,16 +2766,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Abs(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4RecipSqrtApprox(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitF32x4RecipApprox(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) { void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
...@@ -2818,18 +2829,6 @@ void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) { ...@@ -2818,18 +2829,6 @@ void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitS1x4AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
......
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