Commit f4b0d12f authored by Christophe Gisquet's avatar Christophe Gisquet Committed by Diego Biurrun

x86: sbrdsp: Implement SSE neg_odd_64

Timing on Arrandale:
        C   SSE
Win32:  57   44
Win64:  47   38
Unrolling and not storing mask both save some cycles.
Signed-off-by: 's avatarDiego Biurrun <diego@biurrun.de>
parent a862c7d3
......@@ -24,6 +24,7 @@
SECTION_RODATA
; mask equivalent for multiply by -1.0 1.0
ps_mask times 2 dd 1<<31, 0
ps_mask2 times 2 dd 0, 1<<31
ps_neg times 4 dd 1<<31
SECTION_TEXT
......@@ -223,3 +224,24 @@ cglobal sbr_qmf_post_shuffle, 2,3,4,W,z
cmp zq, r2q
jl .loop
REP_RET
INIT_XMM sse
cglobal sbr_neg_odd_64, 1,2,4,z
lea r1q, [zq+256]
.loop:
mova m0, [zq+ 0]
mova m1, [zq+16]
mova m2, [zq+32]
mova m3, [zq+48]
xorps m0, [ps_mask2]
xorps m1, [ps_mask2]
xorps m2, [ps_mask2]
xorps m3, [ps_mask2]
mova [zq+ 0], m0
mova [zq+16], m1
mova [zq+32], m2
mova [zq+48], m3
add zq, 64
cmp zq, r1q
jne .loop
REP_RET
......@@ -32,6 +32,7 @@ void ff_sbr_hf_g_filt_sse(float (*Y)[2], const float (*X_high)[40][2],
void ff_sbr_hf_gen_sse(float (*X_high)[2], const float (*X_low)[2],
const float alpha0[2], const float alpha1[2],
float bw, int start, int end);
void ff_sbr_neg_odd_64_sse(float *z);
void ff_sbr_qmf_post_shuffle_sse(float W[32][2], const float *z);
av_cold void ff_sbrdsp_init_x86(SBRDSPContext *s)
......@@ -39,6 +40,7 @@ av_cold void ff_sbrdsp_init_x86(SBRDSPContext *s)
int mm_flags = av_get_cpu_flags();
if (EXTERNAL_SSE(mm_flags)) {
s->neg_odd_64 = ff_sbr_neg_odd_64_sse;
s->sum_square = ff_sbr_sum_square_sse;
s->sum64x5 = ff_sbr_sum64x5_sse;
s->hf_g_filt = ff_sbr_hf_g_filt_sse;
......
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